7. Calibration
Transceivers include both analog and digital blocks that require calibration to
compensate for process, voltage, and temperature (PVT) variations. Arria 10
transceiver uses hardened Precision Signal Integrity Calibration Engine (PreSICE) to
perform calibration routines.
Power-up Calibration and User Recalibration are the main types of calibration.
• Power-up calibration occurs automatically at device power-up. It runs during
device configuration.
• If you perform dynamic reconfiguration, then you must perform User
Recalibration. In this case, you are responsible for enabling the required
calibration sequence.
Note: If you are recalibrating your ATX PLL or fPLL, follow the ATX PLL-to-ATX PLL or fPLL-to-
ATX PLL spacing guideline as stated in the "Transmit PLLs Spacing Guideline when
using ATX PLLs and fPLLs" chapter.
Arria 10 devices use CLKUSR for transceiver calibration. To successfully complete the
calibration process, the CLKUSR clock must be stable and free running at the start of
FPGA configuration. Also, all reference clocks driving transceiver PLLs (ATX PLL, fPLL,
CDR/CMU PLL) must be stable and free running at start of FPGA configuration. For
more information about CLKUSR pin requirements, refer to the Arria 10 GX, GT, and
SX Device Family Pin Connection Guidelines.
Related Information
• Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs on page 349
• Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
7.1. Reconfiguration Interface and Arbitration with PreSICE
Calibration Engine
In Arria 10 devices, calibration is performed using the Precision Signal Integrity
Calibration Engine (PreSICE). The PreSICE includes an Avalon-MM interface to access
the transceiver channel and PLL programmable registers. This Avalon-MM interface
includes a communication mechanism that enables you to request specific calibration
sequences from the calibration controller.
The PreSICE Avalon-MM interface and user Avalon-MM reconfiguration interface both
share an internal configuration bus. This bus is arbitrated to gain access to the
transceiver channel and PLL programmable registers, and the calibration registers.
UG-01143 | 2018.06.15
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
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