Intel Arria 10 User Manual

Figure 175. x1 Clock Lines
CMU or CDR
CGB
Ch 4
CDR
CGB
Ch 3
CDR
CGB
Ch 2
CGB
Ch 1
CDR
CGB
Ch 0
CDR
CGB
Ch 5
x1 Network
Master
CGB
Master
CGB
ATX PLL1
ATX PLL0
fPLL1
fPLL0
CMU or CDR
3.3.2. x6 Clock Lines
The x6 clock lines route the clock within a transceiver bank. The x6 clock lines are
driven by the master CGB. The master CGB can only be driven by the ATX PLL or the
fPLL. Because the CMU PLLs cannot drive the master CGB, the CMU PLLs cannot be
used for bonding purposes. There are two x6 clock lines per transceiver bank, one for
each master CGB. Any channel within a transceiver bank can be driven by the x6 clock
lines.
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
®
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex