Intel Arria 10 User Manual

For bonded configuration mode, the low speed parallel clock output of the master CGB
is used and the local CGB within each channel is bypassed. For non-bonded
configurations, the master CGB also provides a high speed serial clock output to each
channel without bypassing the local CGB within each channel.
The x6 clock lines also drive the xN clock lines which route the clocks to the
neighboring transceiver banks.
Figure 176. x6 Clock Lines
CGB
Ch 4
CDR
CGB
Ch 3
CDR
CGB
Ch 2
CGB
Ch 1
CDR
CGB
Ch 0
CDR
CGB
Ch 5
Master
CGB
Master
CGB
x6
Top
x6
Bottom
x6
Network
CMU or CDR
CMU or CDR
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
378

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex