Intel Arria 10 User Manual

5.4.3.2. Clock Data Recovery Control
The CDR control feature is used for the L0s fast exit when operating in PIPE Gen3
mode. Upon detecting an Electrical Idle Ordered Set (EIOS), this feature takes manual
control of the CDR by forcing it into a lock-to-reference mode. When an exit from
electrical idle is detected, this feature moves the CDR into lock-to-data mode to
achieve fast data lock.
5.5. Intel Arria 10 Transceiver PHY Architecture Revision History
Document
Version
Changes
2018.06.15 Made the following changes:
• Changed the AC gain settings for high bandwidth and medium bandwidth mode in the "High Gain
Mode" section.
• Added a note about bit slipping to the "RX Gearbox, RX Bitslip, and Polarity Inversion" section.
• Clarified the description of DC gain circuitry in the "Continuous Time Linear Equalization (CTLE)"
section.
• Clarified the description of CTLE manual mode in the "High Data Rate Mode" section.
• Removed the Channel Loss Compensation column from the "Pre-Emphasis Taps" table.
• Updated Serial Loopback Path and Reverse Serial Loopback Path/Pre CDR figures and their notes.
• Changed the instruction in step 1 of the "How to Enable CTLE and DFE" section.
2016.10.31 Made the following changes:
• Added a note below the diagram "Diagnostic Loopback Path/Pre CDR" saying "TX pre-emp is not
supported in pre-CDR loopback. TX pre-emp is recommended to set to zero for all taps."
• "Idle OS Deletion" description updated to "Deletion of Idles occurs in groups of four OS (when there
are two consecutive OS) until the rx_enh_fifo_pfull flag deasserts".
• Removed square wave pattern generator.
2015.05.02 Made the following changes:
• Updated the configuration methods for the CTLE,and DFE schemes in the Arria 10 PMA Architecture
section.
• Removed a signal in the "Gen3 PCS Block Diagram" in the Arria 10 PCI Express Architecture
section.
2015.12.18 Made the following changes:
• Updated the configuration methods for the CTLE, DFE, and adaptation schemes in the Arria 10 PMA
Architecture section.
2015.11.02 Made the following changes to the PMA Architecture section:
• Updated "Channel Pulse Response" figure in the Decision Feedback Equalization (DFE) section.
• Updated the value for the "Number of fixed DFE taps" in the Equalization table in the PMA
Parameters section.
Made the following changes to the Enhanced PCS Architecture section:
• Updated Phase Compensation Mode and Basic Mode sections.
• Added 64B/66B Encoder Reset Condition section.
• Updated TX Gearbox, TX Bitslip and Polarity Inversion sections.
• Updated RX Bitslip in RX Gearbox, RX Bitslip, and Polarity Inversion figure.
• Added “block synchronization” in Enhanced PCS introduction note.
• Updated Enhanced PCS TX FIFO section.
• Updated reference link for TX Phase Compensation Mode section.
• Updated TX Register Mode description.
• Updated Interlaken Frame Generator section description.
• Updated 64B/66B Encoder and Transmitter State Machine section title.
• Updated PRBS Pattern Generator (Shared between Enhanced and Standard) title
• Updated Square Wave Pattern Generator (Shared between Enhanced and Standard)
• Updated RX Register Mode description.
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5. Arria 10 Transceiver PHY Architecture
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex