Document
Version
Changes
Made the following changes to the Standard PCS Architecture section:
• Updated the Byte Serializer section for Serialize x2 and x4 modes.
• Added new figures for 8B/10B Encoder Bit and Byte Reversal features.
2015.05.11 Made the following changes to the PMA Architecture section:
• Updated link to XCVR_A10_RX_TERM_SEL in the "Transmitter Buffer".
• Updated ODI vertical steps to 63 (0 and +/-32) in the "Receiver Buffer".
• Updated CTLE section for adaptation modes. Moved CTLE in the "How to Enable CTLE and DFE"
section.
• Updated VGA section for adaptation modes.
• Updated DFE section for adaptation modes. Moved DFE to the new "How to Enable CTLE and DFE"
section.
• Removed Triggered DFE mode.
• Removed all references related to floating taps.
Made the following changes to the Enhanced PCS Architecture section:
• Updated pattern generators (PRBS, Square Wave and PRP), PRBS Checker and PRP Verifier
sections.
• Revised the descriptions of TX FIFO Fast Register Mode.
• Changed the title and descriptions in "Enhanced PCS Pattern Generators".
• Added new sections for "PRBS Pattern Generator (Shared between Enhanced and Standard PCSes)",
"Square Wave Pattern Generator (Shared between Enhanced and Standard PCSes)", and "Pseudo-
Random Pattern Generator."
• Changed sub title "PRBS Verifier" to "PRBS Checker" and changed their descriptions.
• Changed descriptions in "PRP Verifier".
2014.12.15 Made the following changes to the Enhanced PCS Architecture section:
• Added PRBS7 Generator to support 64-bit width only.
• Updated the rule for tx_enh_data_valid control signal when TX FIFO is used in phase compensation
mode.
Made the following changes to the PCI Express Gen3 PCS Architecture section:
• Updated TX FIFO in Transmitter Datapath.
• Changed the Standard PCS data rate from 12.5 Gbps to 12 Gbps.
Made the following changes to the Standard PCS Architecture section:
• Changed the Standard PCS data rate from 12.5 Gbps to 12 Gbps.
Made the following changes to the PMA Architecture section:
• Added High Speed Differential I/O and Power Distribution Network to the Transmitter Buffer
circuitry.
• Added Power Distribution Network induced Inter-Symbol Interference compensation.
• Replaced the figures related to Programmable Pre Emphasis with a link to Pre Emphasis and Output
Swing Settings Estimator.
2014.08.15 Made the following changes to the PCI Express Gen3 PCS Architecture section:
• Corrected the low latency mode cycles of latency in the TX FIFO (Shared with Standard and
Enhanced PCS).
Made the following changes to the Standard PCS Architecture section:
• Removed the features not supported by 8B/10B Decoder.
• Changed the description of TX FIFO to include the depth of the TX FIFO.
• Updated the description of Polarity Inversion feature to include how to enable Polarity Inversion.
• Updated the description of Pseudo-Random Binary Sequence (PRBS) Generator on the supported
PCS-PMA interface widths.
• Changed the value for Supported Word Aligner Pattern Lengths for Bitslip Mode when the PCS-PMA
Interface Width is 8 in Table 5-8 Word Aligner Pattern Length for Various Word Aligner Modes.
• Changed the description of RX FIFO to include the depth of the RX FIFO.
• Changed the RX Word Aligner pattern length for PCS-PMA interface width 8 in Bitslip Mode.
Made the following changes to the Enhanced PCS Architecture section:
• Changed references from MegaWizard to Parameters Editor.
continued...
5. Arria 10 Transceiver PHY Architecture
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
500