Intel Arria 10 User Manual

Reconfiguration
Address (HEX)
Reconfiguration
Bit
Attribute Name Bit Encoding Description
0x7A [7:0] r_tx_seed_b[7:0] Seed B value
bit[7:0]
0x7B [7:0] r_tx_seed_b[15:8] Seed B value
bit[15:8]
0x7C [7:0] r_tx_seed_b[23:16] Seed B value
bit[23:16]
0x7D [7:0] r_tx_seed_b[31:24] Seed B value
bit[31:24]
0x7E [7:0] r_tx_seed_b[39:32] Seed B value
bit[39:32]
0x7F [7:0] r_tx_seed_b[47:40] Seed B value
bit[47:40]
0x80 [7:0] r_tx_seed_b[55:48] Seed B value
bit[55:48]
0x81 [1:0] r_tx_seed_b[57:56] Seed B value
bit[57:56]
0x82 [0] r_tx_data_pat_sel 1'b0 2 local faults
1'b1 0's
[1] r_tx_test_pat_sel 1'b0 Pseudo Random
[3] r_tx_test_en 1'b1
0x97 [2] r_rx_test_en 1'b1
0xAC [0] r_rx_test_pat_sel 1'b0 Pseudo random
0xD7 [7:0] random_err_cnt[7:0] Error count
0xD8 [7:0] random_err_cnt[7:0]
Related Information
Steps to Perform Dynamic Reconfiguration on page 516
6.17. Timing Closure Recommendations
Intel recommends that you enable the multiple reconfiguration profiles feature in the
Native PHY IP core if any of the modified or target configurations involve changes to
PCS settings. Using multiple reconfiguration profiles is optional if the reconfiguration
involves changes to only PMA settings such as PLL switching, CGB divider switching,
and refclk switching. When you enable multiple reconfiguration profiles, the Quartus
Prime TimeQuest Timing Analyzer includes the necessary PCS timing arcs for all
profiles (initial profile and target profiles) during timing driven compilation. These
timing arcs make the timing more accurate.
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
560

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex