Intel Arria 10 User Manual

Contents
1. Arria
®
10 Transceiver PHY Overview ..............................................................................8
1.1. Device Transceiver Layout......................................................................................9
1.1.1. Arria 10 GX Device Transceiver Layout........................................................ 10
1.1.2. Arria 10 GT Device Transceiver Layout........................................................ 15
1.1.3. Arria 10 GX and GT Device Package Details ................................................ 17
1.1.4. Arria 10 SX Device Transceiver Layout........................................................ 17
1.1.5. Arria 10 SX Device Package Details............................................................ 19
1.2. Transceiver PHY Architecture Overview.................................................................. 20
1.2.1. Transceiver Bank Architecture....................................................................20
1.2.2. PHY Layer Transceiver Components........................................................... 25
1.2.3. Transceiver Phase-Locked Loops................................................................28
1.2.4. Clock Generation Block (CGB)...................................................................29
1.3. Calibration.......................................................................................................... 29
1.4. Intel Arria 10 Transceiver PHY Overview Revision History.......................................... 30
2. Implementing Protocols in Arria 10 Transceivers......................................................... 32
2.1. Transceiver Design IP Blocks................................................................................. 32
2.2. Transceiver Design Flow........................................................................................33
2.2.1. Select and Instantiate the PHY IP Core........................................................33
2.2.2. Configure the PHY IP Core.........................................................................35
2.2.3. Generate the PHY IP Core......................................................................... 36
2.2.4. Select the PLL IP Core.............................................................................. 36
2.2.5. Configure the PLL IP Core........................................................................ 38
2.2.6. Generate the PLL IP Core ......................................................................... 39
2.2.7. Reset Controller ......................................................................................39
2.2.8. Create Reconfiguration Logic..................................................................... 39
2.2.9. Connect the PHY IP to the PLL IP Core and Reset Controller........................... 40
2.2.10. Connect Datapath ................................................................................ 40
2.2.11. Make Analog Parameter Settings ............................................................. 40
2.2.12. Compile the Design................................................................................ 41
2.2.13. Verify Design Functionality...................................................................... 41
2.3. Arria 10 Transceiver Protocols and PHY IP Support....................................................41
2.4. Using the Arria 10 Transceiver Native PHY IP Core.................................................... 45
2.4.1. Presets................................................................................................... 48
2.4.2. General and Datapath Parameters ............................................................. 48
2.4.3. PMA Parameters......................................................................................51
2.4.4. Enhanced PCS Parameters ........................................................................55
2.4.5. Standard PCS Parameters........................................................................ 62
2.4.6. PCS Direct ............................................................................................ 67
2.4.7. Dynamic Reconfiguration Parameters..........................................................67
2.4.8. PMA Ports.............................................................................................. 73
2.4.9. Enhanced PCS Ports................................................................................ 76
2.4.10. Standard PCS Ports................................................................................ 86
2.4.11. IP Core File Locations............................................................................. 91
2.4.12. Unused Transceiver RX Channels.............................................................. 93
2.4.13. Unsupported Features.............................................................................94
2.5. Interlaken..........................................................................................................94
Contents
Intel
®
Arria
®
10 Transceiver PHY User Guide
2

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex