Intel Arria 10 User Manual

2.5.1. Metaframe Format and Framing Layer Control Word.....................................95
2.5.2. Interlaken Configuration Clocking and Bonding............................................97
2.5.3. How to Implement Interlaken in Arria 10 Transceivers.................................103
2.5.4. Design Example..................................................................................... 106
2.5.5. Native PHY IP Parameter Settings for Interlaken........................................ 107
2.6. Ethernet........................................................................................................... 111
2.6.1. Gigabit Ethernet (GbE) and GbE with IEEE 1588v2..................................... 112
2.6.2. 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC
Variants................................................................................................ 124
2.6.3. 10GBASE-KR PHY IP Core .......................................................................135
2.6.4. 1-Gigabit/10-Gigabit Ethernet (GbE) PHY IP Core....................................... 164
2.6.5. 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core.......................................199
2.6.6. XAUI PHY IP Core...................................................................................214
2.6.7. Acronyms.............................................................................................228
2.7. PCI Express (PIPE)............................................................................................ 229
2.7.1. Transceiver Channel Datapath for PIPE......................................................230
2.7.2. Supported PIPE Features......................................................................... 231
2.7.3. How to Connect TX PLLs for PIPE Gen1, Gen2, and Gen3 Modes................... 240
2.7.4. How to Implement PCI Express (PIPE) in Arria 10 Transceivers.................... 246
2.7.5. Native PHY IP Parameter Settings for PIPE ...............................................248
2.7.6. fPLL IP Parameter Core Settings for PIPE................................................... 253
2.7.7. ATX PLL IP Parameter Core Settings for PIPE..............................................255
2.7.8. Native PHY IP Ports for PIPE................................................................... 257
2.7.9. fPLL Ports for PIPE..................................................................................264
2.7.10. ATX PLL Ports for PIPE...........................................................................266
2.7.11. Preset Mappings to TX De-emphasis........................................................267
2.7.12. How to Place Channels for PIPE Configurations......................................... 268
2.7.13. PHY IP Core for PCIe (PIPE) Link Equalization for Gen3 Data Rate............... 274
2.7.14. Using Transceiver Toolkit (TTK)/System Console/Reconfiguration
Interface to manually tune Arria 10 PCIe designs (Hard IP(HIP) and PIPE)
(For debug only).................................................................................... 277
2.8. CPRI................................................................................................................279
2.8.1. Transceiver Channel Datapath and Clocking for CPRI...................................280
2.8.2. Supported Features for CPRI ..................................................................281
2.8.3. Word Aligner in Manual Mode for CPRI.......................................................283
2.8.4. How to Implement CPRI in Arria 10 Transceivers........................................ 284
2.8.5. Native PHY IP Parameter Settings for CPRI............................................... 285
2.9. Other Protocols..................................................................................................289
2.9.1. Using the "Basic (Enhanced PCS)" and "Basic with KR FEC" Configurations
of Enhanced PCS....................................................................................289
2.9.2. Using the Basic/Custom, Basic/Custom with Rate Match Configurations of
Standard PCS........................................................................................ 300
2.9.3. Design Considerations for Implementing Arria 10 GT Channels..................... 319
2.9.4. How to Implement PCS Direct Transceiver Configuration Rule.......................324
2.10. Simulating the Transceiver Native PHY IP Core..................................................... 325
2.10.1. NativeLink Simulation Flow.................................................................... 326
2.10.2. Scripting IP Simulation..........................................................................331
2.10.3. Custom Simulation Flow........................................................................ 332
2.11. Implementing Protocols in Intel Arria 10 Transceivers Revision History.....................335
3. PLLs and Clock Networks............................................................................................ 347
3.1. PLLs................................................................................................................. 349
Contents
Intel
®
Arria
®
10 Transceiver PHY User Guide
3

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex