Intel Arria 10 User Manual

Table 329. Available Options
Value Description
0 – 31 Magnitude 0 – 31
Note: Refer to Arria 10 Pre-Emphasis and Output Swing Settings spreadsheet for selecting
legal pre-emphasis and differential output voltage settings.
Assign To
TX serial data pin.
Syntax
set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL
<value> -to <tx_serial_data pin name>
Related Information
Arria 10 Pre-Emphasis and Output Swing Settings
8.9. Dedicated Reference Clock Settings
8.9.1. XCVR_A10_REFCLK_TERM_TRISTATE
Pin planner or Assignment Editor Name
Dedicated Reference Clock Pin Termination
Description
Specifies if the termination for dedicated reference clock pin is tri-stated. It defaults to
TRISTATE_OFF for non-HCSL cases.
Table 330. Available Options
Value Description
TRISTATE_OFF Internal termination enabled and on-chip biasing circuitry enabled
TRISTATE_ON Internal termination tri-stated. Off-chip termination and biasing circuitry must be implemented
Table 331. Rules
I/O Standard Value
HCSL TRISTATE_ON
CML TRISTATE_OFF
LVPECL TRISTATE_OFF
LVDS TRISTATE_OFF
Assign To
Reference clock pin.
8. Analog Parameter Settings
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
605

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex