Intel Arria 10 User Manual

File Name Description
<your_ip_name> .bsf A Block Symbol File (.bsf) for your Transceiver Native PHY
instance.
<project_dir>/<your_ip_name>/ The directory that stores the HDL files that define the
Transceiver Native PHY IP.
<project_dir>/sim The simulation directory.
<project_dir>/sim/aldec Simulation files for Riviera-PRO simulation tools.
<project_dir>/sim/cadence Simulation files for Cadence simulation tools.
<project_dir>/sim/mentor Simulation files for Mentor simulation tools.
<project_dir>/sim/synopsys Simulation files for Synopsys simulation tools.
<project_dir>/synth The directory that stores files used for synthesis.
The Verilog and VHDL Transceiver Native PHY IP cores have been tested with the
following simulators:
• ModelSim SE
• Synopsys VCS MX
• Cadence NCSim
If you select VHDL for your transceiver PHY, only the wrapper generated by the
Quartus Prime software is in VHDL. All the underlying files are written in Verilog or
SystemVerilog. To enable simulation using a VHDL-only ModelSim license, the
underlying Verilog and SystemVerilog files for the Transceiver Native PHY IP are
encrypted so that they can be used with the top-level VHDL wrapper without using a
mixed-language simulator.
For more information about simulating with ModelSim, refer to the Mentor Graphics
ModelSim and QuestaSim Support chapter in volume 3 of the Quartus Prime
Handbook.
The Transceiver Native PHY IP cores do not support the NativeLink feature in the
Quartus Prime software.
Related Information
• Simulating the Transceiver Native PHY IP Core on page 325
• Mentor Graphics ModelSim and QuestaSim Support
2.4.12. Unused Transceiver RX Channels
To prevent performance degradation of unused transceiver RX channels over time, the
following assignments must be added to an Arria 10 device QSF. You can either use a
global assignment or per-pin assignments.
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON
or
set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to
pin_name
2. Implementing Protocols in Arria 10 Transceivers
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex