Intel Arria 10 User Manual

Related Information
• ATX PLL IP Core on page 354
• fPLL IP Core on page 362
• CMU PLL IP Core on page 370
• Using PLLs and Clock Networks on page 398
2.2.6. Generate the PLL IP Core
After configuring the PLL IP core, complete the following steps to generate the PLL IP
core.
1. Click the Generate HDL button in the Parameter Editor window. The
Generation dialog box opens.
2.
In Synthesis options, under Create HDL design for synthesis select Verilog
or VHDL.
3. Select appropriate Simulation options depending on the choice of the hardware
description language you selected under Synthesis options.
4. In Output Directory, select Clear output directories for selected generation
targets if you want to clear any previous IP generation files from the selected
output directory.
5. Click Generate.
The Quartus
®
Prime software generates a <pll ip core instance name> folder, <pll ip
core instance name>_sim folder, <pll ip core instance name>.qip file, <pll ip core
instance name>.qsys, and <pll ip core instance name>.v file or <pll ip core instance
name>.vhd file. The <pll ip core instance name>.v file is the top level design file for
the PLL IP core and is placed in the <pll ip core instance name>/ synth folder. The
other folders contain lower level design files used for simulation and compilation.
Related Information
IP Core File Locations on page 91
For more information about IP core file structure
2.2.7. Reset Controller
There are two methods to reset the transceivers in Arria 10 devices:
• Use the Transceiver PHY Reset Controller.
• Create your own reset controller that follows the recommended reset sequence.
Related Information
Resetting Transceiver Channels on page 416
2.2.8. Create Reconfiguration Logic
Dynamic reconfiguration is the ability to dynamically modify the transceiver channels
and PLL settings during device operation. To support dynamic reconfiguration, your
design must include an Avalon master that can access the dynamic reconfiguration
registers using the Avalon-MM interface.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
39

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex