Intel Arria 10 User Manual

3.1.4.1. Instantiating CMU PLL IP Core
The CMU PLL IP core for Arria 10 transceivers provides access to the CMU PLLs in
hardware. One instance of the CMU PLL IP core represents one CMU PLL in hardware.
1. Open the Quartus Prime software.
2.
Click Tools ➤ IP Catalog.
3.
In IP Catalog, under Library ➤ Transceiver PLL , select Arria 10 Transceiver
CMU PLL and click Add.
4. In the New IP Instance Dialog Box, provide the IP instance name.
5. Select Arria 10 device family.
6. Select the appropriate device and click OK.
The CMU PLL IP core Parameter Editor window opens.
3.1.4.2. CMU PLL IP Core
Table 240. CMU PLL Parameters and Settings
Parameters Range Description
Message level for rule violations Error
Warning
Specifies the messaging level to use for parameter rule
violations.
• Error - Causes all rule violations to prevent IP
generation.
• Warning - Displays all rule violations as warnings and
allows IP generation in spite of violations.
Bandwidth Low
Medium
High
Specifies the VCO bandwidth.
Higher bandwidth reduces PLL lock time, at the expense of
decreased jitter rejection.
Number of PLL reference clocks 1 to 5 Specifies the number of input reference clocks for the CMU
PLL.
You can use this parameter for data rate reconfiguration.
Selected reference clock source 0 to 4 Specifies the initially selected reference clock input to the
CMU PLL.
TX PLL Protocol mode BASIC
PCIe
This parameter governs the rules for correct protocol
specific settings. Certain features of the PLL are only
available for specific protocol configuration rules. This
parameter is not a preset .
You must set all the other parameters for your protocol.
PLL reference clock frequency Refer to the GUI Selects the input reference clock frequency for the PLL.
PLL output frequency Refer to the GUI Specify the target output frequency for the PLL.
Multiply factor (M-Counter) Read only Displays the M-multiplier value.
Divide factor (N-Counter) Read only Displays the N-counter value.
Divide factor (L-Counter) Read only Displays the L-counter value.
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
370

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English