Intel Arria 10 User Manual

The refclk mux selects the input reference clock to the PLL from the various reference
clock sources available.
N Counter
The N counter divides the refclk mux's output. The N counter division helps lower the
loop bandwidth or reduce the frequency to within the phase frequency detector's
(PFD) operating range. Possible divide ratios are 1 (bypass), 2, 4, and 8.
Phase Frequency Detector (PFD)
The reference clock (refclk) signal at the output of the N counter block and the
feedback clock (fbclk) signal at the output of the M counter block is supplied as an
input to the PFD. The PFD output is proportional to the phase difference between the
two inputs. It aligns the input reference clock (refclk) to the feedback clock
(fbclk). The PFD generates an "Up" signal when the reference clock's falling edge
occurs before the feedback clock's falling edge. Conversely, the PFD generates a
"Down" signal when feedback clock's falling edge occurs before the reference clock's
falling edge.
Charge Pump and Loop Filter (CP + LF)
The PFD output is used by the charge pump and loop filter to generate a control
voltage for the VCO. The charge pump translates the "Up"/"Down" pulses from the
PFD into current pulses. The current pulses are filtered through a low pass filter into a
control voltage which drives the VCO frequency.
Voltage Controlled Oscillator (VCO)
The CMU PLL has a ring oscillator based VCO. For VCO frequency range, refer to the
datasheet.
L Counter
The L counter divides the differential clocks generated by the CMU PLL.
M Counter
The M counter is used in the PFD's feedback path. The output of the L counter is
connected to the M counter. The combined division ratios of the L counter and the M
counter determine the overall division factor in the PFD's feedback path.
Lock Detector (LD)
The lock detector indicates when the CMU PLL is locked to the desired output's phase
and frequency. The lock detector XORs the "Up"/"Down" pulses and indicates when the
M counter's output and N counter's output are phase-aligned.
The reference clock (refclk) and feedback clock (fbclk) are sent to the PCS's ppm
detector block. There is a pre-divider to lower the frequency in case the frequency is
too high.
Related Information
• Calibration on page 567
• IntelArria 10 Device Datasheet
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex