Intel Arria 10 User Manual

The Transceiver PHY Reset Controller IP core connects to the Transceiver PHY and the
Transmit PLL. The Transceiver PHY Reset Controller IP core receives status from the
Transceiver PHY and the Transmit PLL. Based on the status signals or the reset input,
it generates TX and RX reset signals to the Transceiver PHY and TX PLL.
The tx_ready signal indicates whether the TX PMA exits the reset state, and if the TX
PCS is ready to transmit data. The rx_ready signal indicates whether the RX PMA
exits the reset state, and if the RX PCS is ready to receive data. You must monitor
these signals to determine when the transmitter and receiver are out of the reset
sequence.
4.4.1. Parameterizing the Transceiver PHY Reset Controller IP
This section lists steps to configure the Transceiver PHY Reset Controller IP Core in the
IP Catalog. You can customize the following Transceiver PHY Reset Controller
parameters for different modes of operation by clicking Tools ➤ IP Catalog.
To parameterize and instantiate the Transceiver PHY Reset Controller IP core:
1. For Device Family, select your target device from the list.
2.
Click Installed IP ➤ Library ➤ Interface Protocols ➤ Transceiver PHY ➤
Transceiver PHY Reset Controller.
3. Select the options required for your design. For a description of these options,
refer to the Transceiver PHY Reset Controller Parameters.
4. Click Finish. The wizard generates files representing your parameterized IP
variation for synthesis and simulation.
4.4.2. Transceiver PHY Reset Controller Parameters
The Quartus Prime software provides a GUI to define and instantiate a Transceiver PHY
Reset Controller to reset transceiver PHY and external PLL.
Table 247. General Options
Name Range Description
Number of transceiver channels
1-1000
Specifies the number of channels that connect to
the Transceiver PHY Reset Controller IP core. The
upper limit of the range is determined by your
FPGA architecture.
Number of TX PLLs
1-1000
Specifies the number of TX PLLs that connect to
the Transceiver PHY Reset Controller IP core.
Input clock frequency
1-500 MHz
Input clock to the Transceiver PHY Reset Controller
IP core. The frequency of the input clock in MHz.
The upper limit on the input clock frequency is the
frequency achieved in timing closure.
Synchronize reset input On /Off When On, the Transceiver PHY Reset Controller
synchronizes the reset to the Transceiver PHY
Reset Controller input clock before driving it to the
internal reset logic. When Off, the reset input is
not synchronized.
Use fast reset for simulation On /Off When On, the Transceiver PHY Reset Controller
uses reduced reset counters for simulation.
continued...
4. Resetting Transceiver Channels
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
435

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English