Intel Arria 10 User Manual

Name Range Description
Separate interface per
channel/PLL
On /Off When On, the Transceiver PHY Reset Controller
provides a separate reset interface for each
channel and PLL.
TX PLL
Enable TX PLL reset control On /Off When On, the Transceiver PHY Reset Controller IP
core enables the reset control of the TX PLL. When
Off, the TX PLL reset control is disabled.
pll_powerdown duration
1-999999999
Specifies the duration of the PLL powerdown period
in ns. The value is rounded up to the nearest clock
cycle. The default value is 1000 ns.
Synchronize reset input for PLL
powerdown
On /Off When On, the Transceiver PHY Reset Controller
synchronizes the PLL powerdown reset with the
Transceiver PHY Reset Controller input clock. When
Off, the PLL powerdown reset is not synchronized.
TX Channel
Enable TX channel reset control On /Off When On, the Transceiver PHY Reset Controller
enables the control logic and associated status
signals for TX reset. When Off, disables TX reset
control and status signals.
Use separate TX reset per channel On /Off When On, each TX channel has a separate reset.
When Off, the Transceiver PHY Reset Controller
uses a shared TX reset controller for all channels.
TX digital reset mode Auto, Manual, Expose
Port
Specifies the Transceiver PHY Reset Controller
behavior when the pll_locked signal is
deasserted. The following modes are available:
•
Auto—The associated tx_digitalreset
controller automatically resets whenever the
pll_locked signal is deasserted. Intel
recommends this mode.
•
Manual—The associated tx_digitalreset
controller is not reset when the pll_locked
signal is deasserted, allowing you to choose
corrective action.
•
Expose Port—The tx_manual signal is a top-
level signal of the IP core. You can dynamically
change this port to Auto or Manual. (1=
Manual , 0 = Auto)
tx_analogreset duration
1-999999999
Specifies the time in ns to continue to assert
tx_analoglreset after the reset input and all
other gating conditions are removed. The value is
rounded up to the nearest clock cycle.
Note: Model 1 requires this to be set to 70 µs.
Select the Arria 10 Default Settings
preset.
tx_digitalreset duration
1-999999999
Specifies the time in ns to continue to assert the
tx_digitalreset after the reset input and all
other gating conditions are removed. The value is
rounded up to the nearest clock cycle.
Note: Model 1 requires this to be set to 70 µs.
Select the Arria 10 Default Settings
preset. The default value for Model 2 is 20
ns.
pll_locked input hysteresis
0-999999999
Specifies the amount of hysteresis in ns to add to
the pll_locked status input to filter spurious
unreliable assertions of the pll_locked signal. A
continued...
4. Resetting Transceiver Channels
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
436

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English