Intel Arria 10 User Manual

If you set 0x166[7] = 0x1, PreSICE assumes the setting in its memory space is still
valid. If after a rate change you set 0x166[7]=0x0, PreSICE uses the setting from the
Avalon-MM reconfiguration register uploaded from the dynamic reconfiguration
interface or MIF streamed in. After calibration, 0x166[7] = 0x1 is set automatically
and PreSICE uses the settings in its memory space. The rate switch flag only tells
PreSICE where to obtain the CDR charge pump settings for CDR calibration. The rate
switch flag should be used only when there is a rate change.
Multiple MIF files are required for rate change and reconfiguration. When the MIF,
which you want to stream in, has CDR charge pump setting 0x139[7] and 0x133[7:5]
that is different from the previous MIF, you need to recalibrate with 0x166[7]=0x0. If
you stream in the whole MIF, the 0x166[7] is set to the correct value inside the MIF. If
you stream in reduced MIF, you need to check if CDR charge pump setting 0x139[7]
and 0x133[7:5] are inside the reduced MIF or not. If the reduced MIF has CDR charge
pump setting 0x139[7] and 0x133[7:5] updated, you need to set 0x166[7]=0x0, if
the reduced MIF does not include 0x139[7] and 0x133[7:5], you need to set
0x166[7]=0x1.
Table 303. Rate Switch Flag Register for CDR Calibration
Bit Description
0x166[7] Rate switch flag register. Power up default value is 0x1.
0x1, PreSICE uses the default CDR charge pump bandwidth from the default memory
space.
0x0, PreSICE uses the CDR charge pump bandwidth setting from the DPRIO register space.
If you use the Avalon-MM reconfiguration interface to perform a rate change, you
must write 0x0 to 0x166[7] before returning the bus to PreSICE.
7.3. Power-up Calibration
After the device is powered up and programmed, PreSICE automatically initiates the
calibration process. The calibration process may continue during device programming.
The time required after device power-up to complete the calibration process can vary
by device. The total time taken can extend into the user-mode. The cal_busy signals
deassert to indicate the completion of the calibration process. You must ensure that
the transceiver reset sequence in your design waits for the calibration to complete
before resetting the transceiver PLL and the transceiver channel.
The PreSICE may still control the internal configuration bus even after power-up
calibration is complete. You can request access when needed. If a system has an fPLL,
an ATX PLL, and channels, the fPLL cal_busy signal goes low first. The ATX PLL
cal_busy signal goes low after the channels’ tx_cal_busy and rx_cal_busy
signals. Intel recommends that you wait until all *_cal_busy signals are low before
requesting any access.
All power-up calibration starts from Vreg calibration for all banks and channels.
7. Calibration
UG-01143 | 2018.06.15
Intel
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English