Intel Arria 10 - Page 575

Figure 282. Power-up Calibration Sequence for Non-PCIe Hard IP (HIP) Channels
For applications not using PCIe Hard IP, the power-up calibration starts from Vreg calibration for all banks and
channels. Then, PreSICE calibration is done in the sequence as shown in the following figure.
Bank 1
Bank 2
Bank ...
ATX PLL Calibration
Bank 1
Bank 2
Bank ...
fPLL Calibration
Bank 1
Bank 2
Bank ...
RX PMA and TX PMA Calibration
(1)
After All ATX PLLs Calibrated
After All fPLLs Calibrated
(1) CDR and CMU PLL calibration are part of RX
PMA calibration.
For applications using both PCIe Hard IP and non-PCIe channels, the power-up
calibration sequence is:
1. Vreg calibration for all banks and channels.
2. Wait for PCIe reference clock toggle.
3. PCIe Hard IP 0 calibration (if used).
4. PCIe Hard IP 1 calibration (if used).
5. Calibration of all non-PCIe Hard IP channels in calibration sequence.
7. Calibration
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
575