Intel Arria 10 User Manual

6.9. Direct Reconfiguration Flow
Use this flow to perform dynamic reconfiguration when you know exactly which
parameter and value to change for the transceiver channel or PLL. You can use this
flow to change the PMA analog settings, enable/disable PRBS generator, and checker
hard blocks of the transceiver channel.
To perform dynamic reconfiguration using direct reconfiguration flow:
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Read from the desired feature address.
3. Perform a read-modify-write to feature address with a valid value.
4. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Related Information
• Steps to Perform Dynamic Reconfiguration on page 516
• Changing PMA Analog Parameters on page 527
• Using Data Pattern Generators and Checkers on page 550
• Resetting Transceiver Channels on page 416
• Calibration on page 567
• Arria 10 Transceiver Register Map
6.10. Native PHY IP or PLL IP Core Guided Reconfiguration Flow
Use the Native PHY IP core or PLL IP core guided reconfiguration flow to perform
dynamic reconfiguration when you need to change multiple parameters or parameters
in multiple addresses for the transceiver channel or PLL. You can use this flow to
change data rates, change clock divider values, or switch from one PCS datapath to
another. You must generate the required configuration files for the base and modified
Transceiver Native PHY IP core or PLL IP core configurations.
The configuration files contain addresses and bit values of the corresponding
configuration. Compare the differences between the base and modified configuration
files. The differences between these files indicate the addresses and bit values that
must change to switch from one configuration to another. Perform read-modify-writes
for the bit values that are different from the base configuration to obtain the modified
configuration.
To perform dynamic reconfiguration using the IP Guided Reconfiguration Flow:
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Perform a read-modify-write to all addresses and bit values that are different from
the base configuration.
3. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex