If you reconfigured:
• PLLs—Release the reset (analog) of the channel transmitters associated with
the PLL reconfigured.
• TX simplex channels—Release the reset (analog) of the TX channels
reconfigured.
• RX simplex channels—Release the reset (analog) of the RX channels
reconfigured.
• Duplex channels—Release the reset (analog) of the TX and RX channels
reconfigured.
12. Release the channel digital resets either simultaneously or one after another. For
details about releasing the channel resets, refer to "Model 1: Default Model" and
"Model 2: Acknowledgment Model" in the Resetting Transceiver Channels chapter.
(The figures in these sections are for analog resets, but they also contain timing
information about digital resets.)
If you reconfigured:
• PLLs—Release the reset (digital) of the channel transmitters associated with
the PLL reconfigured.
• TX simplex channels—Release the reset (digital) of the TX channels
reconfigured.
• RX simplex channels—Release the reset (digital) of the RX channels
reconfigured.
• Duplex channels—Release the reset (digital) of the TX and RX channels
reconfigured.
Note: You cannot merge multiple reconfiguration interfaces across multiple IP blocks
(merging independent instances of simplex TX/RX into the same physical location or
merging separate CMU PLL and TX channel into the same physical location) when you
use the optional reconfiguration logic soft control registers.
Related Information
• Resetting Transceiver Channels on page 416
• Model 1: Default Model on page 418
• Model 2: Acknowledgment Model on page 427
• Direct Reconfiguration Flow on page 519
• Native PHY IP or PLL IP Core Guided Reconfiguration Flow on page 519
• Reconfiguration Flow for Special Cases on page 521
• Changing PMA Analog Parameters on page 527
• Calibration on page 567
• Arbitration on page 512
• Arria 10 Transceiver Register Map
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
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