Intel Arria 10 User Manual

6. If you are reconfiguring across data rates or protocol modes or enabling/disabling
PRBS, place the channels in analog reset. For details about placing the channel in
analog reset, refer to "Model 1: Default Model" and "Model 2: Acknowledgment
Model" in the Resetting Transceiver Channels chapter.
If you are reconfiguring:
• PLLs—Place the channel transmitter associated with the PLL in reset (analog).
• TX simplex channels—Place the TX channels being reconfigured in reset
(analog).
• RX simplex channels—Place the RX channels being reconfigured in reset
(analog).
• Duplex channels—Place the channel TX and RX being reconfigured in reset
(analog).
7. Check for internal configuration bus arbitration. If PreSICE has control, request
bus arbitration, otherwise go to the next step. For more details, refer to the
"Arbitration" section.
8. Perform the necessary reconfiguration using the flow described in the following
sections:
• Direct Reconfiguration Flow
• Native PHY or PLL IP Guided Reconfiguration Flow
• Reconfiguration Flow for Special Cases
9. Perform all necessary reconfiguration. If reconfiguration involved data rate or
protocol mode changes, then you may have to reconfigure the PMA analog
parameters of the channels. Refer to the Changing PMA Analog Parameters section
for more details.
10. If reconfiguration involved data rate or protocol mode change, then request
recalibration and wait for the calibration to complete. Calibration is complete when
*_cal_busy is deasserted. For more details about calibration registers and the
steps to perform recalibration, refer to the Calibration chapter.
If you reconfigured:
• PLL for data rate change—you must recalibrate the PLL and the channel TX.
• TX simplex channel for data rate change—you must recalibrate the channel
TX.
• RX simplex channel for data rate change—you must recalibrate the channel
RX.
• Duplex channel for data rate change—you must recalibrate the channel TX and
RX.
11. Release the channel analog resets. For details about placing the channel in reset,
refer to "Model 1: Default Model" and "Model 2: Acknowledgment Model" in the
Resetting Transceiver Channels chapter.
6. Reconfiguration Interface and Dynamic Reconfiguration
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex