Intel Arria 10 User Manual

5.2.2.10.5. Basic Mode
In Basic mode, the RX FIFO operates as an elastic buffer, where buffer depths can
vary. This mode allows driving write and read side of RX FIFO with different clock
frequencies. Monitor the FIFO flag to control write and read operations. For RX FIFO,
assert rx_enh_read_en signal with rx_fifo_pfull signal going low.
5.2.2.11. RX KR FEC Blocks
KR FEC Block Synchronization
You can obtain FEC block delineation for the RX KR FEC by locking onto correctly
received FEC blocks with the KR FEC block synchronization. You can also use the KR
FEC up to the maximum transceiver data rate on any protocol that is 64/66-bit
encoded.
Note: The KR FEC block synchronization is available to implement the 10GBASE-KR protocol.
KR FEC Descrambler
The KR FEC descrambler block descrambles received data to regenerate unscrambled
data using the x
58
+ x
39
+1 polynomial. Before the block boundary in the KR FEC sync
block is detected, the data at the input of the descrambler is sent directly to the KR
FEC decoder. When the boundary is detected, the aligned word from the KR FEC sync
block is descrambled with the Pseudo Noise (PN) sequence and then sent to the KR
FEC decoder.
KR FEC Decoder
The KR FEC decoder block performs the FEC (2112, 2080) decoding function by
analyzing the received 32 65-bit blocks for errors. It can correct burst errors of 11 bits
or less per FEC block.
KR FEC RX Gearbox
The KR FEC RX gearbox block adapts the PMA data width to the larger bus width of
the PCS channel. It supports a 64:65 ratio.
Transcode Decoder
The transcode decoder block performs the 65-bit to 64B/66B reconstruction function
by regenerating the 64B/66B synchronization header.
5.3. Arria 10 Standard PCS Architecture
The standard PCS can operate at a data rate of up to 10.8 Gbps. Protocols such as PCI
Express, CPRI 4.2+, GigE, IEEE 1588 are supported in Hard PCS while the other
protocols can be implemented using Basic/Custom (Standard PCS) transceiver
configuration rules.
5. Arria 10 Transceiver PHY Architecture
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
479

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex