2.9.3. Design Considerations for Implementing Arria 10 GT Channels
This section provides information on using the Arria 10 GT transceiver channels .
GT channels can be used in Enhanced PCS basic mode and PCS-Direct configuration to
support 25.8 Gbps. When GT channels are used in PCS-Direct configuration, the PCS
blocks are bypassed. The serializer/deserializer in GT channels supports 64 bit and
128 bit serialization factors.
2.9.3.1. Transceiver PHY IP
Arria 10 GT transceiver channels are implemented using the Native PHY IP with the
Basic (Enhanced PCS) transceiver configuration rule.
• To support 25.8 Gbps, the Enhanced PCS must be configured in basic mode with
the low latency check box unselected. To configure the Enhanced PCS, do not
enable any functional blocks in the Enhanced PCS (that is, disable Block
Synchronizer, Gearbox, Scrambler, and Encoder).
• You can also use the PCS-Direct mode for 25.8 Gbps.
You can bundle several GT transceiver channels with one Native PHY IP instantiation,
but you must instantiate a separate ATX PLL IP for every ATX PLL used.
2.9.3.2. PLL and GT Transceiver Channel Clock Lines
The ATX PLL is used to provide the clock source for the GT transceiver channels. Each
ATX PLL has two dedicated GT clock lines which connect the PLL directly to the GT
transceiver channels within a transceiver bank. The top ATX PLL drives channels 3 and
4, and the bottom ATX PLL drives channels 0 and 1. These connections bypass the rest
of the clock network for higher performance.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
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Arria
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10 Transceiver PHY User Guide
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