Intel Arria 10 - Release Information; Device Family Support

Feature Description
32-bit XGMII for 1G/2.5G/5G/10G (USXGMII).
64-bit XGMII for 10G.
Network-side interface 1.25 Gbps for 1G.
3.125 Gbps for 2.5G.
10.3125 Gbps for 1G/2.5G/5G/10G (USXGMII).
Avalon
®
Memory-Mapped (Avalon-MM)
interface
Provides access to the configuration registers of the PHY.
PCS function 1000BASE-X for 1G and 2.5G.
10GBASE-R for 10G.
USXGMII PCS for 1G/2.5G/5G/10G
Auto-negotiation Implements clause 37. Supported in 1GbE only.
USXGMII Auto-negotiation supported in the 1G/2.5G/5G/10G (USXGMII)
configuration.
IEEE 1588v2 Provides the required latency to the MAC if the MAC enables the IEEE
1588v2 feature.
Sync-E Provides the clock for Sync-E implementation.
2.6.5.1.2. Release Information
Table 152. PHY Release Information
Item Description
Version 16.0
Release Date May 2016
Ordering Codes IP-10GMRPHY
Product ID 00E4
Vendor ID 6AF7
Open Core Plus Supported
2.6.5.1.3. Device Family Support
Device Family
Operating Mode Support Level
Arria 10 2.5G
1G/2.5G
1G/2.5G/5G/10G
Final
Arria V GX/GT/SX/ST 2.5G
1G/2.5G
Final
Other device families No support
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
200