EasyManuals Logo
Home>Intel>Transceiver>Arria 10

Intel Arria 10 User Manual

Intel Arria 10
607 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #502 background imageLoading...
Page #502 background image
6. Reconfiguration Interface and Dynamic
Reconfiguration
This chapter explains the purpose and the use of the Arria 10 reconfiguration interface
that is part of the Transceiver Native PHY IP core and the Transceiver PLL IP cores.
Dynamic reconfiguration is the process of dynamically modifying transceiver channels
and PLLs to meet changing requirements during device operation. Arria 10 transceiver
channels and PLLs are fully customizable, allowing a system to adapt to its operating
environment. You can customize channels and PLLs by dynamically triggering
reconfiguration during device operation or following power-up. Dynamic
reconfiguration is available for Arria 10 Transceiver Native PHY, fPLL, ATX PLL, and
CMU PLL IP cores.
Use the reconfiguration interface to dynamically change the transceiver channel or PLL
settings for the following applications:
Fine tuning signal integrity by adjusting TX and RX analog settings
Enabling or disabling transceiver channel blocks, such as the PRBS generator and
the checker
Changing data rates to perform auto negotiation in CPRI, SATA, or SAS
applications
Changing data rates in Ethernet (1G/10G) applications by switching between
standard and enhanced PCS datapaths
Changing TX PLL settings for multi-data rate support protocols such as CPRI
Changing RX CDR settings from one data rate to another
Switching between multiple TX PLLs for multi-data rate support
The Native PHY and Transmit PLL IP cores provide the following features that allow
dynamic reconfiguration:
Reconfiguration interface
Configuration files
Feature to add PMA analog settings (optional) to the Configuration files (Native
PHY only)
Multiple reconfiguration profiles (Native PHY and ATX PLL)
Embedded reconfiguration streamer (Native PHY and ATX PLL)
Altera Debug Master Endpoint (ADME)
Optional reconfiguration logic
UG-01143 | 2018.06.15
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the Intel Arria 10 and is the answer not in the manual?

Intel Arria 10 Specifications

General IconGeneral
BrandIntel
ModelArria 10
CategoryTransceiver
LanguageEnglish

Related product manuals