Intel Arria 10 - Configuration Registers

For the 1G/2.5G/5G/10G operating mode, constrain the PHY for the 10G datapath as
well as the 1G/2.5G datapath. Refer to the example provided:
<Installation Directory>/ip/altera/ethernet/alt_mge_phy/example/
alt_mge_phy_multi_speed_10g.sdc.
2.6.5.2.3. Changing the PHY's Speed
You can change the PHY's speed through the reconfiguration block.
1. The user application initiates the speed change by writing to the corresponding
register of the reconfiguration block.
2. The reconfiguration block performs the following steps:
• In Arria 10 devices:
a.
Sets the xcvr_mode signal of the 1G/2.5G/5G/10G Multi-rate Ethernet
PHY IP core to the requested speed.
b. Reads the generated .mif file for the configuration settings and configures
the transceiver accordingly.
The .mif files, alt_mge_phy_reconfig_parameters_CFG*.mif, are
generated in the <IP working directory>/
altera_xcvr_native_a10_<version>/synth/reconfig directory.
c. Selects the corresponding transceiver PLL.
d. Triggers the transceiver recalibration.
3. The reconfiguration block triggers the PHY reset through the transceiver reset
controller.
2.6.5.3. Configuration Registers
You can access the 16-bit configuration registers via the Avalon-MM interface. These
configuration registers apply only to 2.5G and 1G/2.5G operating modes.
Observe the following guidelines when accessing the registers:
• Do not write to reserved or undefined registers.
• When writing to the registers, perform read-modify-write to ensure that reserved
or undefined register bits are not overwritten.
Table 155. PHY Register Definitions
Addr Name Description Access HW Reset
Value
0x00
control
•
Bit [15]: RESET. Set this bit to 1 to trigger a soft
reset.
The PHY clears the bit when the reset is completed.
The register values remain intact during the reset.
RWC 0
•
Bit[14]: LOOPBACK. Set this bit to 1 to enable
loopback on the serial interface.
RW 0
•
Bit [12]: AUTO_NEGOTIATION_ENABLE. Set this bit
to 1 to enable auto-negotiation.
Auto-negotiation is supported only in 1GbE.
Therefore, set this bit to 0 when you switch to a
speed other than 1GbE.
RW 0
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
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Arria
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10 Transceiver PHY User Guide
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