7.2.4. ATX PLL Calibration Registers
Table 299. ATX PLL Calibration Registers
Bit ATX PLL Calibration Enable Register Offset Address 0x100
0 ATX PLL calibration enable. Set 1 to enable calibration.
1 Reserved
During calibration when reconfig_waitrequest is high, you cannot read or write
calibration enable registers.
To enable calibration, you must perform a read-modify-write on offset address 0x100.
The following steps are an example of how to enable the ATX PLL calibration enable
bit:
1. Read the offset address 0x100.
2. Keep the value from MSB[7:1] and set LSB[0] to 1.
3. Write new value to offset address 0x100.
7.2.5. Capability Registers
Capability registers allow you to read calibration status through the Avalon-MM
reconfiguration interface. They are soft logic and reside in the FPGA fabric.
Reading capability registers does not require bus arbitration. You can read them
during the calibration process.
To use capability registers to check calibration status, you must enable the capability
registers when generating the Native PHY or PLL IP cores. To enable the capability
registers, select the Enable capability registers option in the Dynamic
Reconfiguration tab.
The tx_cal_busy and rx_cal_busy signals from the hard PHY are from the same
hardware and change state (high/low) concurrently during calibration. The register
bits 0x281[5:4] are defined to solve this issue. This prevents a TX channel being
affected by RX calibration, or an RX channel being affected by TX calibration. This
feature cannot be enabled, when a Simplex TX and Simplex RX channel merging is
involved. To merge a Simplex TX and a Simplex RX channel into one physical channel,
refer to Dynamic Reconfiguration Interface Merging Across Multiple IP Blocks on page
542.
7. Calibration
UG-01143 | 2018.06.15
Intel
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10 Transceiver PHY User Guide
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