Intel Arria 10 User Manual

3.4. Clock Generation Block
In Arria 10 devices, there are two types of clock generation blocks (CGBs)
• Local clock generation block (local CGB)
• Master clock generation block (master CGB)
Each transmitter channel has a local clock generation block (CGB). For non-bonded
channel configurations, the serial clock generated by the transmit PLL drives the local
CGB of each channel. The local CGB generates the parallel clock used by the serializer
and the PCS.
There are two standalone master CGBs within each transceiver bank. The master CGB
provides the same functionality as the local CGB within each transceiver channel. The
output of the master CGB can be routed to other channels within a transceiver bank
using the x6 clock lines. The output of the master CGB can also be routed to channels
in other transceiver banks using the xN clock lines. Each transmitter channel has a
multiplexer to select its clock source from either the local CGB or the master CGB.
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
383

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English