Intel Arria 10 - Page 382

Figure 178. GT Clock Lines
CMU or CDR
CGB
Ch 4
CDR
CGB
Ch 3
CDR
CGB
Ch 2
CGB
Ch 1
CDR
CGB
Ch 0
CDR
CGB
Ch 5
ATX PLL1
ATX PLL0
CMU or CDR
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
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10 Transceiver PHY User Guide
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