Intel Arria 10 User Manual

Steps to implement fPLL to fPLL cascading:
1. Instantiate the fPLL IP core. Refer to Instantiating the fPLL IP Core on page 362
for detailed steps.
2. Set the following configuration settings for the fPLL IP core in the Parameter
Editor:
• Set the fPLL Mode to Cascade Source.
• Set the Desired output clock frequency.
3. Instantiate the fPLL IP core (the second PLL in PLL cascading configuration). Refer
to Instantiating the fPLL IP Core on page 362 for detailed steps.
4. Configure the second fPLL IP core for the desired data rate and the reference clock
frequency. Set reference clock frequency for the second fPLL same as the output
frequency of the first fPLL.
5. Connect the fPLL IP core (cascade source) to fPLL IP core (transceiver PLL) as
shown in the above figure. Ensure the following connections:
•
The fPLL has an output port hssi_pll_cascade_clk. Connect this port to
the second fPLL's pll_refclk0 port.
6. Set the source (upstream) fPLL bandwidth to Low setting and the destination
(downstream) fPLL bandwidth to High setting.
7. If the input reference clock is available at device power-up, the first PLL is
calibrated during the power-up calibration. The second PLL need to be
recalibrated. Refer to the User Recalibration section. If the input reference clock is
not available at device power-up, then re-run the calibration for the first PLL. After
the first PLL has been calibrated, re-calibrate the second PLL.
Notes:
• No special configuration is required for the Native PHY instance.
• ATX PLL to fPLL cascading mode is added to address the OTN and SDI jitter
requirement. In this mode, ATX PLL generates a relatively high and clean
reference frequency in fractional mode. The reference is driving the fPLL, which is
running in integer mode. Overall cascaded two PLLs, synthesize a needed
frequency for a given data rate.
Related Information
User Recalibration on page 576
3.11.4. Mix and Match Example
In the Arria 10 transceiver architecture, the separate Native PHY IP core and the PLL
IP core scheme allows great flexibility. It is easy to share PLLs and reconfigure data
rates. The following design example illustrates PLL sharing and both bonded and non-
bonded clocking configurations.
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex