Intel Arria 10 User Manual

Acronym Definition
LD Local Device.
LT Link training in backplane Ethernet Clause 72 for 10GBASE-KR and 40GBASE-KR4.
LP Link partner, to which the LD is connected.
MAC Media Access Control.
MII Media independent interface.
OSI Open System Interconnection.
PCS Physical Coding Sublayer.
PHY Physical Layer in OSI 7-layer architecture, also in Intel device scope is: PCS + PMA.
PMA Physical Medium Attachment.
PMD Physical Medium Dependent.
SGMII Serial Gigabit Media Independent Interface.
WAN Wide Area Network.
XAUI 10 Gigabit Attachment Unit Interface.
2.7. PCI Express (PIPE)
You can use Arria 10 transceivers to implement a complete PCI Express solution for
Gen1, Gen2, and Gen3, at data rates of 2.5, 5.0, and 8 Gbps, respectively.
Configure the transceivers for PCIe functionality using one of the following methods:
• Arria 10 Hard IP for PCIe
This is a complete PCIe solution that includes the Transaction, Data Link, and
PHY/MAC layers. The Hard IP solution contains dedicated hard logic, which
connects to the transceiver PHY interface.
Note: For more information, refer to the Arria 10 Avalon-ST Interface for PCIe
Solutions User Guide.
• Native PHY IP Core in PIPE Gen1/Gen2/Gen3 Transceiver Configuration
Rules
Use the Native PHY IP (Native PHY IP Core) to configure the transceivers in PCIe
mode, giving access to the PIPE interface (commonly called PIPE mode in
transceivers). This mode enables you to connect the transceiver to a third-party
MAC to create a complete PCIe solution.
The PIPE specification (version 3.0) provides implementation details for a PCIe-
compliant physical layer. The Native PHY IP Core for PIPE Gen1, Gen2, and Gen3
supports x1, x2, x4, or x8 operation for a total aggregate bandwidth ranging from
2 to 64 Gbps. In a x1 configuration, the PCS and PMA blocks of each channel are
clocked and reset independently. The x2, x4, and x8 configurations support
channel bonding for two-lane, four-lane, and eight-lane links. In these bonded
channel configurations, the PCS and PMA blocks of all bonded channels share
common clock and reset signals.
Gen1 and Gen2 modes use 8B/10B encoding, which has a 20% overhead to overall
link bandwidth. Gen3 modes use 128b/130b encoding, which has an overhead of less
than 2%. Gen1 and Gen2 modes use the Standard PCS, and Gen3 mode uses the
Gen3 PCS for its operation.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
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Arria
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English