Intel Arria 10 User Manual

Table 223. Valid Permutations for GT and GX Channel Configuration in Transceiver Bank
GXBL1G for Channels 0, 1, and 2
GT Transceiver Channel Configuration A Configuration B Configuration C Configuration D
Ch2 Unusable Unusable Unusable GX
Ch1 GT GT Unusable GX
Ch0 GT Unusable GT GX
Notes on grouping channels Ch0, Ch1, and Ch2:
• If channels 0 and 1 are configured as GT channels, channel 2 is unusable
(Configuration A).
• If either channel 0 or 1 is configured as a GT channel, the remaining channels are
unusable (Configurations B and C).
• If channels 0 and 1 are not configured as GT channels, this grouping can be all
configured as GX channels (Configuration D).
• If either channel 0 or 1 is used as a GT channel, then the ATX PLL adjacent to
channel 0 and 1 must be reserved for GT channel configurations.
Table 224. Valid Permutations for GT and GX Channel Configuration in Transceiver Banks
GXBL1E and GXBL1H for Channels 3, 4, and 5
GT Transceiver Channel Configuration A Configuration B Configuration C Configuration D
Ch5 Unusable Unusable Unusable GX
Ch4 GT GT Unusable GX
Ch3 GT Unusable GT GX
Notes on grouping channels Ch3, Ch4, and Ch5:
• If channels 3 and 4 are configured as GT channels, channel 5 is unusable
(Configuration A).
• If either channel 3 or 4 is configured as a GT channel, the remaining channels are
unusable (Configurations B and C).
• If channels 3 and 4 are not configured as GT channels, this grouping can be all
configured as GX channels (Configuration D).
• If either channel 3 or 4 is used as a GT channel, then the ATX PLL adjacent to
channel 3 and 4 must be reserved for GT channel configurations.
2.9.4. How to Implement PCS Direct Transceiver Configuration Rule
You should be familiar with PCS Direct architecture, PMA architecture, PLL
architecture, and the reset controller before implementing PCS Direct Transceiver
Configuration Rule.
1. Open the IP Catalog and select Arria 10 Transceiver Native PHY IP. Refer to
Select and Instantiate the PHY IP Core on page 33 for detailed steps.
2. Select PCS Direct from the Transceiver configuration rules list located under
Datapath Options.
3. Configure your Native PHY IP.
4. Click Generate to generate the Native PHY IP (this is your RTL file).
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex