Figure 163. ATX PLL IP with GT Clock Lines Enabled
7. Create a transceiver reset controller. Refer to Resetting Transceiver Channels on
page 416 for more details about configuring the reset IP core.
8. Connect the Native PHY IP core to the PLL IP core and the reset controller.
The ATX PLL's port tx_serial_clk_gt represents the dedicated GT clock lines.
Connect this port to the Native PHY IP core's tx_serial_clk0 port. The Quartus
Prime software automatically uses the dedicated GT clocks instead of the x1 clock
network.
2.9.3.5. Arria 10 GT Channel Usage
All Arria 10 GT devices have a total of six GT transceiver channels to support 25.8
Gbps.
Arria 10 GT devices have three transceiver banks that support up to two GT channels.
Each channel can operate as a duplex channel, TX only, or RX only channel.
Transceiver banks GXBL1E and GXBL1H each contain two GT transceiver channels:
Ch3 and Ch4. Transceiver bank GXBL1G contains two GT transceiver channels: Ch0
and Ch1. Channels 2 and 5 on any bank can only be configured as GX transceiver
channels.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
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