Intel Arria 10 - Page 322

Figure 162. Signals and Ports of the Native PHY for Basic (Enhanced PCS) Transceiver
Configuration Rule for Data Rates Above 17.4 Gbps and FPGA Fabric / PCS
Interface width of 128 bits
Reconfiguration
Registers
NIOS
Hard Calibration IP
TX PMA
Serializer
tx_serial_data
tx_serial_clk0
(from TX PLL)
rx_cal_busy
tx_cal_busy
rx_serial_data
rx_control[19:0]
rx_cdr_refclk0
rx_is_lockedtodata
rx_is_lockedtoref
rx_parallel_data[127:0]
tx_control[17:0] tx_control[17:0]
tx_digital_resettx_digital_reset
tx_parallel_data[127:0]
reconfig_clk
reconfig_avmm
reconfig_reset
tx_coreclkin
tx_clkout
tx_enh_data_valid
tx_parallel_data[127:0]
tx_coreclkin
tx_clkout
tx_enh_data_valid
RX PMA
TX Enhanced PCS
RX Enhanced PCS
Deserializer
refclk
CDR
rx_clkout
rx_coreclkin
rx_clkout
rx_coreclkin
rx_analog_reset
tx_analog_reset
rx_digital_resetrx_digital_reset
rx_parallel_data[127:0]
rx_control[19:0]
5.
Select Tools ➤ IP Catalog ➤ Basic Functions ➤ Clocks ➤ PLLs and Resets ➤
PLL ➤ Arria 10 Transceiver ATX PLL. Refer to Instantiating the ATX PLL IP Core
on page 354 for detailed steps.
6. Configure the ATX PLL IP using the Parameter Editor.
• Select the GT clock output buffer.
• Enable the PLL GT clock output port.
• Set the PLL output clock frequency to the Native PHY IP recommended
frequency.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
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10 Transceiver PHY User Guide
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