Intel Arria 10 User Manual

Note: • GT channel bonding is not supported.
• For optimum performance of GT channel, the reference clock of ATX PLL is
recommended to be from a dedicated reference clock pin in the same bank.
Related Information
Input Reference Clock Sources on page 372
2.9.3.3. Reset Controller
Each GT channel instantiated has independent analog and digital reset ports. Refer to
the Resetting Transceiver Channels chapter for more details on designing a reset
controller to reset these ports.
Related Information
Resetting Transceiver Channels on page 416
Reset controller general information and implementation details
2.9.3.4. How to Implement Designs for Data Rates Above 17.4 Gbps Using
Enhanced PCS in Low Latency Mode
• You should be familiar with the Enhanced PCS and PMA architecture, PLL
architecture, and the reset controller.
• Make sure you have selected an Arria 10 GT device for the project
1.
Select Tools ➤ IP Catalog ➤ Interface Protocols ➤ Transceiver PHY ➤ Arria
10 Transceiver Native PHY. Refer to Select and Instantiate the PHY IP Core on
page 33 for detailed steps.
2. Set VCCR_GXB and VCCT_GXB to 1.1V. Note these settings are overridden by
the QSF file settings which should also be set to 1.1V. QII makes sure the actual
voltage prescribed is in line with pin connection guidelines and the Arria10 Data
Sheet.
3. Select Basic (Enhanced PCS) from the Transceiver configuration rules list
located under Datapath Options.
4. Use the parameter values in the tables in Transceiver Native PHY IP Parameters
Settings for Basic (Enhanced PCS) and Basic with KR FEC for each input of the
Arria 10 Transceiver Native PHY Parameter Editor as a starting point. Or, you can
use the protocol presets described in Transceiver Native PHY Presets. You can then
modify the settings to meet your specific requirements.
• Ensure that the data rate is set to 25781.25 Mbps. To achieve the higher data
rates, use Enhanced PCS basic mode with the low latency option unchecked.
Select a CDR reference clock to match your data rate. Use Phase
compensation FIFO modes.
• Make sure DFE is disabled from Rx PMA settings.
• Set the Enhanced PCS / PMA interface width to 64 bits.
• Set the FPGA fabric / Enhanced PCS interface width to 64 bits.
• You can enable RX/TX FIFO double width mode to create a FPGA fabric / PCS
interface width of 128 bits.
• Click Finish to generate the Native PHY IP (this is your RTL file).
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
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Arria
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex