Figure 125. Connection Guidelines for a Basic with KR FEC Transceiver Design
Design
Testbench
64d + 2c
PLL IP Core
Reset
Controller
Arria 10 Transceiver
Native PHY
8. Simulate your design to verify its functionality.
Related Information
• Arria 10 Enhanced PCS Architecture on page 461
For more information about Enhanced PCS architecture
• Arria 10 PMA Architecture on page 447
For more information about PMA architecture
• Using PLLs and Clock Networks on page 398
For more information about implementing PLLs and clocks
• PLLs on page 349
PLL architecture and implementation details
• Resetting Transceiver Channels on page 416
Reset controller general information and implementation details
• Enhanced PCS Ports on page 76
For detailed information about the available ports in the Basic protocol.
2.9.1.2. Native PHY IP Parameter Settings for Basic (Enhanced PCS) and Basic
with KR FEC
This section contains the recommended parameter values for this protocol. Refer to
Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter
values.
Table 211. General and Datapath Parameters
The first two sections of the Parameter Editor for the Transceiver Native PHY provide a list of general and
datapath options to customize the transceiver.
Parameter
Range
Message level for rule violations error, warning
Transceiver configuration rules Basic (Enhanced PCS), Basic w/KR FEC
PMA configuration rules Basic, QPI, GPON
Transceiver mode TX / RX Duplex, TX Simplex, RX Simplex
Number of data channels 1 to 96
Data rate GX transceiver channel: 1 Gbps
(48)
to 17.4 Gbps
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
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®
10 Transceiver PHY User Guide
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