Intel Arria 10 User Manual

• Interlaken on page 94
• Gigabit Ethernet (GbE) and GbE with IEEE 1588v2 on page 112
• 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants on
page 124
• 10GBASE-KR PHY IP Core on page 135
• 1-Gigabit/10-Gigabit Ethernet (GbE) PHY IP Core on page 164
• PCI Express (PIPE) on page 229
• CPRI on page 279
• Using the "Basic (Enhanced PCS)" and "Basic with KR FEC" Configurations of
Enhanced PCS on page 289
• Using the Basic/Custom, Basic/Custom with Rate Match Configurations of Standard
PCS on page 300
• Design Considerations for Implementing Arria 10 GT Channels on page 319
2.2.3. Generate the PHY IP Core
After configuring the PHY IP, complete the following steps to generate the PHY IP.
1. Click the Generate HDL button in the Parameter Editor window. The
Generation dialog box opens.
2.
In Synthesis options, under Create HDL design for synthesis select Verilog
or VHDL.
3. Select appropriate Simulation options depending on the choice of the hardware
description language you selected under Synthesis options.
4. In Output Directory, select Clear output directories for selected generation
targets if you want to clear any previous IP generation files from the selected
output directory.
5. Click Generate.
The Quartus Prime software generates a <phy ip instance name> folder, <phy ip
instance name>_sim folder, <phy ip instance name>.qip file, <phy ip instance
name>.qsys file, and <phy ip instance name>.v file or <phy ip instance name>.vhd
file. This <phy ip instance name>.v file is the top level design file for the PHY IP and is
placed in the <phy ip instance name>/synth folder. The other folders contain lower
level design files used for simulation and compilation.
Related Information
IP Core File Locations on page 91
For more information about IP core file structure
2.2.4. Select the PLL IP Core
Arria 10 devices have three types of PLL IP cores:
• Advanced Transmit (ATX) PLL IP core.
• Fractional PLL (fPLL) IP core.
• Channel PLL / Clock Multiplier Unit (CMU) PLL IP core.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
36

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex