Intel Arria 10 User Manual

Figure 236. Enhanced PCS Datapath Diagram
Transmitter Enhanced PCSTransmitter PMA
Receiver PMA
Receiver Enhanced PCS
TX
Gearbox
tx_serial_data
Serializer
Interlaken
Disparity Generator
Scrambler
Parallel Clock
PRBS
Generator
PRP
Generator
rx_serial_data
Deserializer
CDR
Descrambler
Interlaken
Disparity Checker
Block
Synchronizer
Interlaken
Frame Sync
RX
Gearbox
PRBS
Verifier
Transcode
Decoder
KR FEC RX
Gearbox
KR FEC
Decoder
KR FEC
Block Sync
KR FEC
Descrambler
Parallel Clock
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Clock Divider
Parallel and Serial Clocks
Clock Generation Block (CGB)
Serial Clock
Input Reference Clock
ATX PLL
fPLL
CMU PLL
64B/66B Decoder
and RX SM
10GBASE-R
BER Checker
PRP
rx_pma_div_clkout
tx_pma_div_clkout
Verifier
rx_coreclkin
rx_clkout
Enhanced PCS
TX FIFO
Enhanced PCS
RX FIFO
Interlaken
Frame Generator
Interlaken
CRC32 Generator
Interlaken
CRC32 Checker
64B/66B Encoder
and TX SM
TX
Data &
Control
RX
Data &
Control
FPGA
Fabric
tx_coreclkin
tx_clkout
KR FEC
TX Gearbox
KR FEC
Scrambler
KR FEC
Encoder
Transcode
Encoder
Related Information
Implementing Protocols in Arria 10 Transceivers on page 32
5.2.1. Transmitter Datapath
5.2.1.1. Enhanced PCS TX FIFO
The Enhanced PCS TX FIFO provides an interface between the transmitter channel PCS
and the FPGA fabric. The TX FIFO can operate for phase compensation between the
channel PCS and FPGA fabric. You can also use the TX FIFO as an elastic buffer to
control the input data flow, using tx_enh_data_valid. The TX FIFO also allows
channel bonding. The TX FIFO has a width of 73 bits and a depth of 16 words.
You can set the TX FIFO partially full and empty thresholds through the Transceiver
and PLL Address Map. Refer to the Reconfiguration Interface and Dynamic
Reconfiguration chapter for more details.
The TX FIFO supports the following operating modes:
• Phase Compensation mode
• Register mode
• Interlaken mode
• Basic mode
Related Information
Reconfiguration Interface and Dynamic Reconfiguration on page 502
5. Arria 10 Transceiver PHY Architecture
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
462

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English