Intel Arria 10 User Manual

Figure 41. 24 Lanes Bonded Interlaken Link, RX Direction
To show more details, three different time segments are shown with different zoom level.
rx_clkout[0]
rx_digitalreset
rx_ready
rx_enh_blk_lock
rx_enh_frame_lock
rx_enh_fifo_pfull[0]
rx_enh_fifo_pfull
rx_enh_fifo_pempty
rx_enh_fifo_align_clr
rx_enh_fifo_align_val
rx_enh_fifi_rd_en
rx_enh_data_valid
rx_parallel_data
rx_control
24`h00000024`hffffff
24`h000000
24`hffffff
24`h000000
24`h000000
24`h000000
24`h000000
24`h000000
24`h000000
24`h000000
1536`h0100009c0100
240`h0441104411044
24`hffffff
24`hffffff
24`h00000124`h0...
24`h000000
24`hffffff
24`h000000
24`h00...
24`h000000
24`h000000
1536`h0100009c0100009c0100009c0100009c0100009c0100009c0100009c01000
240`h044110441104404411044110441104411044110441104411044110441104411
24`hfffffe
24`h000001
24`h000000
24`hffffff
24`hffffff
24`h000000
24`hffffff
24`hffffff
24`hffffff
24`h000000
24`hffffff
24`h000000
24`hffffff
24`h00..
24`h000000
24`h000000
1536`h01000...
240`h044110...
24`h000000 24`h000000
24`hffffff 24`hffffff24`h00..
24`hffffff 24`hffffff
24`h00..
1536`h1e...
240`h90a... 240`h826...
rx_ready
Asserted
24`h00...
24`hff...
Some Lanes pfull Signal Is Asserted
before All Lanes pempty is Deasserted;
RX Deskew Fails. Need to Realign
Assert align_clr
to Re-Align
All Lanes pfull Low and All
Lanes pempty Deasserted
RX Deskew Complete
Start Reading Data
Based on FIFO Flags
24`h00..
Related Information
• Arria 10 Enhanced PCS Architecture on page 461
For more information about Enhanced PCS architecture
• Arria 10 PMA Architecture on page 447
For more information about PMA architecture
• Using PLLs and Clock Networks on page 398
For more information about implementing PLLs and clocks
• PLLs on page 349
PLL architecture and implementation details
• Resetting Transceiver Channels on page 416
Reset controller general information and implementation details
• Enhanced PCS Ports on page 76
For detailed information about the available ports in the Interlaken protocol
2.5.4. Design Example
Intel provides a PHY layer-only design example to help you integrate an Interlaken
PHY into your complete design.
The TX soft bonding logic is included in the design example. Intel recommends that
you integrate this module into your design.
The Interlaken Design Example is available on the Arria 10 Transceiver PHY Design
Examples Wiki page.
Note: The design examples on the Wiki page provide useful guidance for developing your
own designs, but they are not guaranteed by Intel. Use them with caution.
Related Information
Interlaken Design Example
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English