Intel Arria 10 - Native PHY IP Parameter Settings for CPRI

Figure 120. Connection Guidelines for a CPRI PHY Design
PLL IP Core
Data
Generator
Data
Verifier
Arria 10 Transceiver Native PHY
Reset Controller
rx_cdr_refclk
tx_serialclk0
pll_locked
pll_sel
reset
clk
pll_refclk
tx_ready
rx_ready
tx_parallel_data
tx_clkout
rx_parallel_data
rx_clkout
tx_serial_data
rx_serial_data
rx_is_lockedtodata rx_cal_busy tx_cal_busy tx_analogreset tx_digitalreset rx_analogreset rx_digitalreset
pll_cal_busy
8. Simulate your design to verify its functionality.
Related Information
• Arria 10 Standard PCS Architecture on page 479
For more information about Standard PCS architecture
• Arria 10 PMA Architecture on page 447
For more information about PMA architecture
• Using PLLs and Clock Networks on page 398
For more information about implementing PLLs and clocks
• PLLs on page 349
PLL architecture and implementation details
• Resetting Transceiver Channels on page 416
Reset controller general information and implementation details
• Standard PCS Ports on page 86
Port definitions for the Transceiver Native PHY Standard Datapath
2.8.5. Native PHY IP Parameter Settings for CPRI
Table 205. General and Datapath Options
The first two sections of the Parameter Editor for the Native PHY IP provide a list of general and datapath
options to customize the transceiver.
Parameter
Value
Message level for rule violations error
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
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10 Transceiver PHY User Guide
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