Intel Arria 10 User Manual

Port Range Clock Domain Description
pll_refclk3
input N/A Reference clock input port 3.
pll_refclk4
input N/A Reference clock input port 4.
tx_serial_clk
output N/A High speed serial clock output port for
GX channels. Represents the x1 clock
network.
pll_locked
output Asynchronous Active high status signal which
indicates if PLL is locked.
reconfig_clk0
input N/A Optional Avalon interface clock. Used
for PLL reconfiguration. The
reconfiguration ports appear only if the
Enable Reconfiguration parameter is
selected in the PLL IP Core GUI. When
this parameter is not selected, the
ports are set to OFF internally.
reconfig_reset0
input
reconfig_clk0
Used to reset the Avalon interface.
Asynchronous to assertion and
synchronous to deassertion.
reconfig_write0
input
reconfig_clk0
Active high write enable signal.
reconfig_read0
input
reconfig_clk0
Active high read enable signal.
reconfig_address0[9:0]
input
reconfig_clk0
10-bit address bus used to specify
address to be accessed for both read
and write operations.
reconfig_writedata0[31:0]
input
reconfig_clk0
32-bit data bus. Carries the write data
to the specified address.
reconfig_readdata0[31:0]
output
reconfig_clk0
32-bit data bus. Carries the read data
from the specified address.
reconfig_waitrequest0
output
reconfig_clk0
Indicates when the Avalon interface
signal is busy. When asserted, all
inputs must be held constant.
pll_cal_busy
output Asynchronous Status signal that is asserted high
when PLL calibration is in progress.
Perform logical OR with this signal and
the tx_cal_busy port on the reset
controller IP.
Related Information
• Calibration on page 29
• Reconfiguration Interface and Dynamic Reconfiguration on page 502
• Avalon Interface Specifications
The ports related to reconfiguration are compliant with the Avalon
Specification. Refer to the Avalon Specification for more details about these
ports.
3.2. Input Reference Clock Sources
The transmitter PLL and the clock data recovery (CDR) block need an input reference
clock source to generate the clocks required for transceiver operation. The input
reference clock must be stable and free-running at device power-up for proper PLL
calibrations.
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
372

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex