Intel Arria 10 User Manual

For ATX PLL VCO frequencies between 11.4 GHz and 14.4 GHz, when two ATX PLLs
operate at the same VCO frequency (within 100 MHz) and drive GX channels, they
must be placed 4 ATX PLLs apart (skip 3).
For ATX PLL VCO frequencies between 11.4 GHz and 14.4 GHz, when two ATX PLLs
operate at the same VCO frequency (within 100 MHz) and drive GT channels, they
must be placed 3 ATX PLLs apart (skip 2).
For two ATX PLLs providing the serial clock for PCIe/PIPE Gen3, they must be placed 4
ATX PLL apart (skip 3).
Note: If these spacing rules are violated, Intel Quartus Prime issues a critical warning.
When two ATX PLLs are being used, and you meet the following two conditions in your
applications:
• One of the ATX PLL re-calibration process is triggered.
• The other channel (that is clocked by another ATX PLL) is in data transmission
mode.
You must place the two ATX PLLs 7 ATX PLLs apart (skip 6). ATX PLLs between the 2
active ATX PLLs should not be used.
ATX PLL-to-fPLL Spacing Guidelines
If you are using both ATX PLL and fPLL, and you meet the below two conditions in
your applications:
• When ATX PLL VCO frequency and fPLL VCO frequency is within 50MHz.
• ATX PLL is used to drive protocol which includes OTU2, OTU2e, SDH/Sonet_9953/
OC192/STM64, 10G GPON or protocol that has jitter integration start range
<1MHz and data rate > 3Gbps.
The ATX PLL and fPLL must be separated at least by 1 ATX PLL in between.
If you are using both ATX PLL and fPLL, and you meet the below two conditions in
your applications:
• fPLL user re-calibration process is triggered.
• ATX PLL is used to drive protocol which includes OTU2, OTU2e, SDH/Sonet_9953/
OC192/STM64, 10G GPON or protocol that has jitter integration start range
<1MHz and data rate > 3Gbps.
then the ATX PLL and fPLL must be separated at least by 1 ATX PLL in between
(regardless of the ATX PLL and fPLL VCO frequency offset).
3.1.2. ATX PLL
The ATX PLL contains LC tank-based voltage controlled oscillators (VCOs). These LC
VCOs have different frequency ranges to support a continuous range of operation.
When driving the Transceiver directly, the ATX PLL only supports the integer mode. In
cascade mode, the ATX PLL only supports fractional mode.
3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Intel
®
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex