Intel Arria 10 User Manual

• Bit Mappings When the Simplified Interface Is Disabled on page 263
2.7.6. fPLL IP Parameter Core Settings for PIPE
Table 188. Parameter Settings for Arria 10 fPLL IP core in PIPE Gen1, Gen2, Gen3 modes
This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10
Transceiver Native PHY IP Core for the full range of parameter values.
Parameter Gen1 PIPE Gen2 PIPE Gen3 PIPE (For Gen1/
Gen2 speeds)
PLL
General
fPLL mode Transceiver Transceiver Transceiver
Protocol Mode PCIe Gen 1 PCIe Gen 2 PCIe Gen 2
Message level for rule
violation
Error Error Error
Number of PLL reference
clocks
1 1 1
Selected reference clock
source
0 0 0
Enable fractional mode Disable Disable Disable
Enable manual counter
configuration
Disable Disable Disable
Enable ATX to fPLL cascade
clock input port
Disable Disable Disable
Settings
Bandwidth Low, Medium, High Low, Medium, High Low, Medium, High
Feedback
Operation mode Direct Direct Direct
Output frequency
Transceiver usage
PLL output frequency 250oMHz 2500MHz 2500MHz
PLL datarate 2500Mbps 5000Mbps 5000Mbps
PLL integer reference clock
frequency
100 MHz, 125 MHZ 100 MHz, 125 MHZ 100 MHz, 125 MHZ
Master Clock Generation Block (MCGB)
Include master clock
generation block
Disable for x1
Enable for x2, x4, x8
Disable for x1
Enable for x2, x4, x8
Disable for x1
Disable for x2, x4, x8
Clock division factor N/A for x1
1 for x2, x4, x8
N/A for x1
1 for x2, x4, x8
N/A for x1
N/A for x2, x4, x8
Enable x6/xN non-bonded
high-speed clock output port
N/A for x1
Disable for x2, x4, x8
N/A for x1
Disable for x2, x4, x8
N/A for x1
N/A for x2,x4, x8
Enable PCIe clock switch
interface
N/A for x1
Disable for x2, x4, x8
N/A for x1
Enable for x2, x4, x8
N/A for x1
N/A for x2, x4, x8
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
253

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex