Intel Arria 10 User Manual

Port Direction Clock Domain Description
3'b111 - Receive disparity error, not used if
disparity error is reported using 3'b100.
pipe_sw[1:0]
Out N/A
Signal to clock generation buffer indicating
the rate switch request. Use this signal for
bonding mode only.
For non-bonded applications this signal is
internally connected to the local CGB.
Active High. Refer to Table 191 on page 263
Bit Mappings When the Simplified Interface is
Disabled for more details.
Table 191. Bit Mappings When the Simplified Interface Is Disabled
This section contains the recommended settings for this protocol. Refer to Using the Arria 10 Transceiver
Native PHY IP Core for the full range of parameter values.
Signal Name Gen1 (TX Byte
Serializer and RX
Byte Deserializer
disabled)
Gen1 (TX Byte
Serializer and RX Byte
Deserializer in X2
mode), Gen2 (TX Byte
Serializer and RX Byte
Deserializer in X2
mode)
Gen3
tx_parallel_data tx_parallel_dat
a[7:0]
tx_parallel_data[29
:22,7:0]
tx_parallel_data[40:33,29:22,18
:11,7:0]
tx_datak tx_parallel_dat
a[8]
tx_parallel_data[30
,8]
tx_parallel_data[41,30,19,8]
pipe_tx_compliance tx_parallel_dat
a[9]
tx_parallel_data[31
,9]
tx_parallel_data[42,31,20,9]
pipe_tx_elecidle tx_parallel_dat
a[10]
tx_parallel_data[32
,10]
tx_parallel_data[43,32,21,10]
pipe_tx_detectrx_loop
bacK
tx_parallel_dat
a[46]
tx_parallel_data[46
]
tx_parallel_data[46]
pipe_powerdown tx_parallel_dat
a[48:47]
tx_parallel_data[48
:47]
tx_parallel_data[48:47]
pipe_tx_margin tx_parallel_dat
a[51:49]
tx_parallel_data[51
:49]
tx_parallel_data[51:49]
pipe_tx_swing tx_parallel_dat
a[53]
tx_parallel_data[53
]
tx_parallel_data[53]
rx_parallel_data rx_parallel_dat
a[7:0]
rx_parallel_data[39
:32,7:0]
rx_parallel_data[55:48,39:32,23
:16,7:0]
rx_datak rx_parallel_dat
a[8]
rx_parallel_data[40
,8]
rx_parallel_data[56,40,24,8]
rx_syncstatus rx_parallel_dat
a[10]
rx_parallel_data[42
,10]
rx_parallel_data[58,42,26,10]
pipe_phy_status rx_parallel_dat
a[65]
rx_parallel_data[65
]
rx_parallel_data[65]
pipe_rx_valid rx_parallel_dat
a[66]
rx_parallel_data[66
]
rx_parallel_data[66]
pipe_rx_status rx_parallel_dat
a[69:67]
rx_parallel_data[69
:67]
rx_parallel_data[69:67]
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
263

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex