Intel Arria 10 User Manual

Port Direction Clock Domain Description
rx_datak[3:0], [1:0], or
[0]
Out
rx_coreclkin
The data and control indicator.
For Gen1 or Gen2, when 0, indicates that
rx_parallel_data is data, when 1,
indicates that rx_parallel_data is
control.
For Gen3, Bit[0] corresponds to
rx_parallel_data[7:0], Bit[1]
corresponds to rx_parallel_data[15:8],
and so on. Refer to tableBit Mappings When
the Simplified Interface is Disabled for more
details.
pipe_rx_sync_hdr[(2N-1)
:0]
Out
rx_coreclkin
For Gen3, indicates whether the 130-bit
block being transmitted is a Data or Control
Ordered Set Block. The following encodings
are defined:
2'b10: Data block
2'b01: Control Ordered Set block
This value is read when
pipe_rx_blk_start = 4'b0001. Refer to
Section 4.2.2.1. Lane Level Encoding in the
PCI Express Base Specification, Rev. 3.0 for
a detailed explanation of data transmission
and reception using 128b/130b encoding and
decoding.
pipe_rx_blk_start[(N-1)
:0]
Out
rx_coreclkin
For Gen3, specifies the start block byte
location for RX data in the 128-bit block
data. Used when the interface between the
PCS and PHY-MAC (FPGA Core) is 32 bits.
Not used for Gen1 and Gen2 data rates.
Active High
pipe_rx_data_valid[(N-1
):0]
Out
rx_coreclkin
For Gen3, this signal is deasserted by the
PHY to instruct the MAC to ignore
rx_parallel_data for current clock cycle.
A value of 1'b1 indicates the MAC should use
the data. A value of 1'b0 indicates the MAC
should not use the data.
Active High
pipe_rx_valid[(N-1):0]
Out
rx_coreclkin
Asserted when RX data and control are valid.
pipe_phy_status[(N-1):
0]
Out
rx_coreclkin
Signal used to communicate completion of
several PHY requests.
Active High
pipe_rx_elecidle[(N-1):
0]
Out Asynchronous
When asserted, the receiver has detected an
electrical idle.
Active High
pipe_rx_status[(3N-1):
0]
Out
rx_coreclkin
Signal encodes receive status and error
codes for the receive data stream and
receiver detection. The following encodings
are defined:
3'b000 - Receive data OK
3'b001 - 1 SKP added
3'b010 - 1 SKP removed
3'b011 - Receiver detected
3'b100 - Either 8B/10B or 128b/130b decode
error and (optionally) RX disparity error
3'b101 - Elastic buffer overflow
3'b110 - Elastic buffer underflow
continued...
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
262

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex