Intel Arria 10 User Manual

PLLs when configured in clock multiplier unit (CMU) mode. The channel PLLs of
channel 0, 2, 3, and 5 cannot be configured in CMU mode and therefore cannot be
used as transmit PLLs.
Related Information
• CMU PLL on page 368
For more information on CMU PLL.
• CMU PLL IP Core on page 370
For information on implementing CMU PLL IP.
1.2.4. Clock Generation Block (CGB)
In Arria 10 devices, there are two types of clock generation blocks (CGBs):
• Master CGB
• Local CGB
Transceiver banks with six transceiver channels have two master CGBs. Master CGB1
is located at the top of the transceiver bank and master CGB0 is located at the bottom
of the transceiver bank. Transceiver banks with three channels have only one master
CGB. The master CGB divides and distributes bonded clocks to a bonded channel
group. It also distributes non-bonded clocks to non-bonded channels across the x6/xN
clock network.
Each transceiver channel has a local CGB. The local CGB is used for dividing and
distributing non-bonded clocks to its own PCS and PMA blocks.
Related Information
Clock Generation Block on page 383
For more information on clock generation block.
1.3. Calibration
Arria 10 FPGAs contain a dedicated calibration engine to compensate for process
variations. The calibration engine calibrates the analog portion of the transceiver to
allow both the transmitter and receiver to operate at optimum performance.
The CLKUSR pin clocks the calibration engine. All transceiver reference clocks and the
CLKUSR clock must be free running and stable at the start of FPGA configuration to
successfully complete the calibration process and for optimal transceiver performance.
Note:
For more information about CLKUSR electrical characteristics, refer to IntelArria 10
Device Datasheet. The CLKUSR can also be used as an FPGA configuration clock. For
information about configuration requirements for the CLKUSR pin, refer to the
Configuration, Design Security, and Remote System Upgrades in Arria 10 Devices
chapter in the Arria 10 Core Fabric and General-Purpose I/O Handbook. For more
information about calibration, refer to the Calibration chapter. For more information
about CLKUSR pin requirements, refer to the IntelArria 10 GX, GT, and SX Device
Family Pin Connection Guidelines.
Related Information
• IntelArria 10 Device Datasheet
1. Arria
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10 Transceiver PHY Overview
UG-01143 | 2018.06.15
Intel
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Arria
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex