Intel Arria 10 User Manual

When using the byte deserializer, additional logic is required in the FPGA fabric to
determine if the comma byte is received in the lower or upper byte of the word. The
delay is dependent on the word in which the comma byte appears.
2.8.3. Word Aligner in Manual Mode for CPRI
When configuring the word aligner in CPRI (Manual), the word aligner parses the
incoming data stream for a specific alignment character. After rx_digitalreset
deasserts, asserting the rx_std_wa_patternalign triggers the word aligner to look
for the predefined word alignment pattern or its complement in the received data
stream. It is important to note that the behavior of the word aligner in Manual mode
operates in different ways depending on the PCS-PMA interface width.
Table 204. Word Aligner Signal Status Behaviors in Manual Mode
PCS-PMA Interface Width
rx_std_wa_patternalign
Behavior
rx_syncstatus Behavior rx_patterndetect
Behavior
10 Level sensitive One parallel clock cycle (When
three control patterns are
detected)
One parallel clock cycle
20 Edge sensitive Remains asserted until next
rising edge of
rx_std_wa_patternalign
One parallel clock cycle
PCS-PMA Width = 10
When the PCS-PMA interface width is 10, 3 consecutive word alignment patterns found
after the initial word alignment in a different word boundary causes the word aligner
to resynchronize to this new word boundary if the rx_std_wa_patternalign
remains asserted; rx_std_wa_patternalign is level sensitive. If you deassert
rx_std_wa_patternalign, the word aligner maintains the current word boundary
even when it finds the alignment pattern in a new word boundary. When the word
aligner is synchronized to the new word boundary, rx_patterndetect and
rx_syncstatus are asserted for one parallel clock cycle.
PCS-PMA Width =20
When the PMA-PCS width is 20, any alignment pattern found after the initial alignment
in a different word boundary causes the word aligner to resynchronize to this new
word boundary on the rising edge of rx_std_wa_patternalign;
rx_std_wa_patternalign is edge sensitive. The word aligner maintains the current
word boundary until the next rising edge of rx_std_wa_patternalign. When the
word aligner is synchronized to the new word boundary, rx_patterndetect asserts
for one parallel clock cycle and rx_syncstatus remains asserted until the next rising
edge of rx_std_wa_patternalign.
Figure 118. Word Aligner in Manual Alignment Mode Waveform
rx_std_wa_patternalign
rx_parallel_data
rx_patterndetect
rx_syncstatus
rx_clkout
0...
0
0000
f1e4b6e4 b9dbf1db 915d061d e13f913f 7a4ae24a bcbc7b78 bcbcbcbc
1100
1100
1111
1111 0000
95cd3c50 91c295cd ded691c2
Related Information
Word Aligner on page 485
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
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®
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex