Intel Arria 10 User Manual

To avoid transmission interference in time division multiplexed systems, every radio in
a cell network requires accurate delay estimates with minimal delay uncertainty. Lower
delay uncertainty is always desired for increased spectrum efficiency and bandwidth.
The Arria 10 devices are designed with features to minimize the delay uncertainty for
both RECs and REs.
2.8.2.1. Word Aligner in Deterministic Latency Mode for CPRI
The deterministic latency state machine in the word aligner reduces the known delay
variation from the word alignment process. It automatically synchronizes and aligns
the word boundary by slipping one half of a serial clock cycle (1UI) in the deserializer.
Incoming data to the word aligner is aligned to the boundary of the word alignment
pattern (K28.5).
Figure 116. Deterministic Latency State Machine in the Word Aligner
Deserializer To 8B/10B Decoder
Clock-Slip
Control
Parallel
Clock
From RX CDR
Deterministic Latency
Synchronization State Machine
When using deterministic latency state machine mode, assert
rx_std_wa_patternalign to initiate the pattern alignment after the reset sequence
is complete. This is an edge-triggered signal in all cases except one: when the word
aligner is in manual mode and the PMA width is 10, in which case
rx_std_wa_patternalign is level sensitive.
Figure 117. Word Aligner in Deterministic Mode Waveform
rx_clkout
rx_std_wa_patternalign
rx_parallel_data
rx_errdetect
rx_disperr
rx_patterndetect
rx_syncstatus
f1e4b6e4
1101
1101
0000
0000
0000
0000
1010
1010
1000
1000
0010
0000
1010
1010
0000
0000
1111
1111
0000
b9dbf1db 915d061d e13f913f 7a4ae24a bbae9b10 bcbcbcbc 95cd3c50 91c295cd
Related Information
Word Aligner on page 485
2.8.2.1.1. Transmitter and Receiver Latency
The latency variation from the link synchronization function (in the word aligner block)
is deterministic with the rx_bitslipboundaryselectout port. Additionally, you
can use the tx_bitslipboundaryselect port to fix the round trip transceiver
latency for port implementation in the remote radio head to compensate for latency
variation in the word aligner block. The tx_bitslipboundaryselect port is
available to control the number of bits to be slipped in the transmitter serial data
stream. You can optionally use the tx_bitslipboundaryselect port to round the
round-trip latency to a whole number of cycles.
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
282

Intel Arria 10 Specifications

General

Brand	Intel
Model	Arria 10
Category	Transceiver
Language	English