Intel Arria 10 User Manual

6.16. Using Data Pattern Generators and Checkers
The Arria 10 transceivers contain hardened data generators and checkers to provide a
simple and easy way to verify and characterize high speed links. Hardening the data
generators and verifiers saves FPGA fabric logic resources. The pattern generator
block supports the following patterns:
• Pseudo Random Binary Sequence (PRBS)
• Pseudo Random Pattern (PRP)
The pattern generators and checkers are supported only for non-bonded channels.
6.16.1. Using PRBS Data Pattern Generator and Checker
Use the Arria 10 PRBS generator and checker to simulate traffic and easily
characterize high-speed links without fully implementing any upper protocol stack
layer. The PRBS generator generates a self-aligning pattern and covers a known
number of unique sequences. Because the PRBS pattern is generated by a Linear
Feedback Shift Register (LFSR), the next pattern can be determined from the previous
pattern. When the PRBS checker receives a portion of the received pattern, it can
generate the next sequence of bits to verify whether the next data sequence received
is correct.
The PRBS generator and checker are shared between the Standard and Enhanced
datapaths through the PCS. Therefore, they have only one set of control signals and
registers. The data lines from the various PCSs and shared PRBS generator are MUXed
before they are sent to the PMA. When the PRBS generator is enabled, the data on the
PRBS data lines is selected to be sent to the PMA. Either the data from the PCS or the
data generated from the PRBS generator can be sent to the PMA at any time.
The PRBS generator and checker can be configured for two widths of the PCS-PMA
interface: 10 bits and 64 bits. PRBS9 is available in both 10-bit and 64-bit PCS-PMA
widths. All other PRBS patterns are available in 64-bit PCS-PMA width only. The PRBS
generator and checker patterns can only be used when the PCS-PMA interface width is
configured to 10 bits or 64 bits. For any other PCS-PMA width, to ensure the correct
clocks are provided to the PRBS blocks you must first reconfigure the width to either
10 or 64 bits before using the PRBS generator and checker. For example, when the
transceiver is configured to a 20-bit PCS/PMA interface, you must first reconfigure the
PCS-PMA width to 10 bits before setting up the PRBS generator and checker. The PRBS
setup does not automatically change the PCS/PMA width.
The 10-bit PCS-PMA width for PRBS9 is available for lower frequency testing. You can
configure PRBS9 in either 10-bit or 64-bit width, based on the data rate. The FPGA
fabric-PCS interface must run in the recommended speed range of the FPGA core.
Therefore, you must configure PRBS9 in one of the two bit width modes, so that the
FPGA fabric-PCS interface parallel clock runs in this operating range.
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
Intel
®
Arria
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10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex