Intel Arria 10 User Manual

Examples:
• If you want to use PRBS9 and the data rate is 2.5 Gbps, you can use the PRBS9 in
10-bit mode (PCS-PMA width = 10). In this case, the parallel clock frequency =
Data rate / PCS-PMA width = 2500 Mbps/10 = 250 MHz.
• If you want to use PRBS9 and the data rate is 6.4 Gbps, you can use the PRBS9 in
64-bit mode (PCS-PMA width = 64). In this case, the parallel clock frequency =
Data rate / PCS-PMA width = 6400 Mbps/64 = 100 MHz.
• If you want to use PRBS9 and the data rate is 12.5 Gbps, you can use the PRBS9
in 64 bit mode (PCS-PMA width = 64). In this case, the parallel clock frequency =
Data rate / PCS-PMA width = 12500 Mbps/64 = 195.3125 MHz.
Table 291. PRBS Supported Polynomials and Data Widths
Use the 10-bit mode of PRBS9 when the data rate is lower than 3 Gbps.
Pattern Polynomial 64-Bit 10-Bit
PRBS7 G(x) = 1+ x
6
+ x
7
X
PRBS9 G(x) = 1+ x
5
+ x
9
X X
PRBS15 G(x) = 1+ x
14
+ x
15
X
PRBS23 G(x) = 1+ x
18
+ x
23
X
PRBS31 G(x) = 1+ x
28
+ x
31
X
The PRBS checker has the following control and status signals available to the FPGA
fabric:
•
rx_prbs_done—Indicates the PRBS sequence has completed one full cycle. It
stays high until you reset it with rx_prbs_err_clr.
•
rx_prbs_err—Goes high if an error occurs. This signal is pulse-extended to
allow you to capture it in the RX FPGA CLK domain.
•
rx_prbs_err_clr—Used to reset the rx_prbs_err signal.
Enable the PRBS checker control and status ports through the Native PHY IP
Parameter Editor in the Quartus Prime software.
Use the PRBS soft accumulators to count the number of accumulated bits and errors
when the hard PRBS blocks are used. For more information about using the
accumulators and reading the error values, refer to the PRBS Soft Accumulators
section.
Table 292. Register Map for PRBS Generators for bonded and non bonded designs
Reconfigur
ation
Address
(HEX)
Reconfigur
ation Bit
Attribute Name Related
Addresses
Attribute
Encoding
Bit
Encoding
Description
0x006 [2:0] tx_pma_data_sel 0x8 prbs_pat 3'b100 Select PRBS Generator
Block
[3] prbs9_dwidth prbs9_10b 1'b1 Enable PRBS9 in 10-bit
mode
prbs9_64b 1'b0 Enable PRBS9 in 64-bit
mode
continued...
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
Intel
®
Arria
®
10 Transceiver PHY User Guide
551

Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex