Intel Arria 10 User Manual

Note: You must ensure that none of the profiles in the Native PHY IP and ATX PLL IP
Parameter Editor gives error messages, or else IP generation fails. The Native PHY IP
core and ATX PLL IP only validates the current active profile dynamically. For example,
if you store a profile with error messages in the Native PHY IP or ATX PLL IP Parameter
Editor and load another profile without any error messages, the error messages
disappear in the IP. You are then allowed to generate the IP, but the generation fails.
Related Information
• Steps to Perform Dynamic Reconfiguration on page 516
• Timing Closure Recommendations on page 560
• Analog Parameter Settings on page 585
6.5. Embedded Reconfiguration Streamer
You can optionally enable the embedded reconfiguration streamer in the Native PHY IP
core, ATX PLL IP core, or both to automate the reconfiguration operation.
The embedded reconfiguration streamer is a feature block that can perform Avalon-
MM transactions to access channel/ATX PLL configuration registers in the transceiver.
When you enable the embedded streamer, the Native PHY/ATX PLL IP cores embed the
reconfiguration profiles and reconfiguration control logic in the IP files.
For the ATX PLL IP, you can control the embedded streamer block through the
reconfiguration interface. Control and status signals of the streamer block are memory
mapped in the PLL’s soft control and status registers.
Table 265. Control and Status Register Memory Map for Embedded Reconfiguration
Streamer in ATX PLL IP
Reconfigura
tion
Address
(hex)
Reconfigura
tion Bit
Attribute
Name
Attribute
Description
Bit
Encoding
Transceiver Block Description
340 7 cfg_load Start
streaming
1'b1 Embedded
Reconfiguration
Streamer
Set to 1'b1 to initiate
streaming, self-clearing bit
[2:0] cfg_sel Configuratio
n profile
select
Direct
mapped
Embedded
Reconfiguration
Streamer
Binary encoding of the
configuration Profile to
stream
341 0 rcfg_busy Busy Status
bit
1'b1 Embedded
Reconfiguration
Streamer
Bit is set to:
• 1'b1—streaming is in
progress
• 1'b0—streaming is
complete
Note: The soft control and status registers at x340 and x341 are enabled when you enable
the embedded reconfiguration streamer in the ATX PLL IP core.
Refer to Steps to Perform Dynamic Reconfiguration for a complete list of steps to
perform dynamic reconfiguration using the IP guided reconfiguration flow with
embedded streamer enabled. To perform a reference clock switching, use the
reconfiguration flow for special cases described in Steps to Perform Dynamic
Reconfiguration.
6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
Intel
®
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®
10 Transceiver PHY User Guide
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Intel Arria 10 Specifications

General

Transceiver Data Rate	Up to 17.4 Gbps
Transceiver Protocols Supported	CPRI, JESD204B
Transceiver Power Consumption	Varies depending on configuration and data rate. Refer to Intel Arria 10 device power estimation tools.
Transceiver Features	Clock data recovery
Power Consumption per Channel	Varies depending on data rate and equalization settings. Refer to Intel Arria 10 device power estimation tools.
Transceiver Type	FPGA integrated transceiver
Operating Temperature Range	-40°C to 100°C (Industrial)
Number of Transceiver Channels	up to 96 full-duplex